JPH06224893A - Clock signal extracting circuit - Google Patents

Abstract

PURPOSE:To provide the miniaturized clock signal extracting circuit by letting the output signal of an inverted OR circuit and the output signal of an inverted AND circuit be the clock signals of two phases. CONSTITUTION:Corresponding to a prescribed clock term T, delay time equal to an (n+1/2)-fold period (2n+1)T/2 is set to a first delay circuit 6. The delay time equal to that of the first delay circuit 6 is set to both of second and third delay circuits 9 and 11. In this case, since a circuit composed of a NOR gate 8 and the second delay circuit 9 becomes a sort of feedback oscillation circuit to be oscillated in a period T/2 by having a feedback loop, a clock signal Sck synchronized to the prescribed clock period T with high fidelity is formed. On the other hand, when an inverse phase signal generated at a terminal Pf is alternately logically inverted synchronously with the period T/2, a signal Sckb to be generated at a terminal Pq is turned to the inverted signal of the inverse phase signal generated at the terminal Pf.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal extraction circuit which is applied to a receiver or the like in a digital transmission system and reproduces a clock signal from a received NRZ digital signal.

[0002]

2. Description of the Related Art Conventionally, as such a clock signal extraction circuit, one disclosed in Japanese Patent Publication No. 3-101411 is known. This circuit, as shown in FIG. 1 of the publication, uses input data as an exclusive OR gate (Ex
-OR gate) (2) is directly input to one input terminal (A), and the input data is passed through a delay element (1) having a delay time (T) equal to a clock period to an Ex-OR gate.
Input to the other input terminal (B) of (2), and further, Ex-OR
The exclusive OR output (C) of the gate (2) is connected to the OR gate (O
R gate) (3) Input to one input terminal of
The OR gate outputs the output signal (E) of the R gate (3) through a delay element (4) having a delay time (T) equal to the clock period.
The circuit configuration is such that the output signal (E) is extracted as a clock signal by feeding back to the other input terminal (D) of (3).

The delay element (1) and the Ex-OR gate
The first-stage circuit consisting of (2) is "PHASE-LOCKED LOOP CIRCUI
T DESIGH '' Dan H. Wolaver Prentice Hall P.213 ~ 216
It is also disclosed in Fig.10-4 (a).

By the way, in the clock signal extracting circuit of Japanese Patent Publication No. 3-101411, the delay element (1) and
The delay time (T) in (4) is set to be equal to the period of the clock signal. The delay elements (1) and (4) are generally capacitors having a predetermined time constant, and the delay time (T) is determined by the time constant.

However, applying a capacitor to obtain the delay time in this way, for example, when the clock signal extraction circuit is realized as an integrated circuit device (IC, LSI, etc.), the capacitor in the semiconductor chip is Since the area occupancy becomes high, there arises a problem that it is difficult to reduce the size of the integrated circuit device.

Therefore, the inventor of the present application sets the delay time of the delay element to 1/2 of the cycle (T) of the clock signal to be reproduced, that is, T / 2, so that even a small-capacity capacitor can be used as a clock. We have researched and developed a clock signal extraction circuit that enables signal extraction.

As a result, a clock signal extraction circuit as shown in FIGS. 3 and 5 was devised. First, in the clock signal extraction circuit shown in FIG. 3, a digital signal S _in transferred from a transmission line of a digital communication system or the like is input to one input terminal of an exclusive OR gate (Ex-NOR gate) 1. a to the input terminal a of the Ex-NOR gate 1 and then input to the other input terminal b of the Ex-NOR gate 1
The first stage circuit is configured to input the digital signal S _in through the delay circuit 2 having a delay time (T / 2) of 2 cycles. Further, an exclusive OR output (NOR gate) 3 for inputting the exclusive OR output generated by the Ex-NOR gate 1 to one input terminal c and an output signal S _ck generated at the output terminal d of the NOR gate 3 are output. A post-stage circuit including a delay circuit 4 for delaying the delay time (T / 2) and feeding back to the other input terminal e of the NOR gate 3 is provided.

According to such a clock signal extraction circuit, the signal waveform generated at the input / output terminal of each element is as shown in the timing chart of FIG. 4, for example. That is, as shown in the figure as an example, "1" synchronized with the clock cycle T
0100110010 "NRZ (non-return zero)
If the digital signal S _in is received, the signal at the terminal a is the same as the digital signal S _in, and the signal at the terminal b is a signal delayed by T / 2 from that, so that the Ex-NOR
The output of the gate 1 (that is, the signal of the terminal c) is "010101011101110111010" synchronized with the cycle of T / 2.
Further, the signal S _ck generated at the output d of the NOR gate 3 is the inverted logical sum of the signals at the terminals e and c, and therefore is “101010” synchronized with the cycle of T / 2.
10000100010001010 ″. Then, this signal S _ck becomes the finally extracted clock signal.

However, in this clock signal extraction circuit, the digital signal S _in and the clock signal S _in FIG.
_As can be understood by comparing _ck , the digital signal S _in continuously has the logic “1” over the period T or more.
When it becomes or becomes a logic "0" continuously, there is a problem that the clock signal S _ck is not reproduced as shown in cycles τ ₁ , τ ₂ , and τ ₃ , and a clock synchronized with the cycle T occurs. A flaw was observed that did not faithfully reproduce the signal _Sck .

On the other hand, the clock signal extraction circuit shown in FIG. 5 has a structure in which the NOR gate 3 in FIG. 3 is replaced with an OR gate (OR gate) 5. According to this circuit, as shown in FIG. 6, the signals generated at the input / output terminals a, b and c of the Ex-NOR gate 1 are the same as those in FIG. 4, but the logic of the signal at the terminal c is once "1". When it becomes "terminal d
Also becomes a logic "1" and the logic of the signal at the terminal e also becomes "1" after the delay time T / 2. Therefore, the clock signal S _ck is fixed at the logic "1" of the signal at the terminal e. That is, even if the logic of the terminal c changes according to the digital signal S _{in, the} OR gate 5 continues to output the logic “1” of the signal of the terminal e as it is, so that the clock signal S _ck synchronized with the cycle T is output.
Was found to be not faithfully reproduced.

[0011]

SUMMARY OF THE INVENTION In the course of such research and development, the present invention has a small clock signal extraction circuit capable of faithfully extracting a clock signal from a received digital signal, which is the original purpose. The purpose is to provide.

Further, the above-mentioned prior art extracts the one-phase clock signal S _ck , but does not extract the two-phase clock signals which are in the opposite phase with each other in synchronization with the clock cycle. There is a drawback that it cannot be applied to a circuit or the like that operates with a two-phase clock signal. Therefore, another object is to provide a clock signal extraction circuit that solves this drawback and generates a two-phase clock signal.

[0013]

In order to achieve such an object, the present invention synchronizes a NRZ-coded digital signal in synchronization with a predetermined clock period (T) to the clock period (T). In a clock signal extraction circuit for extracting a clock signal, the digital signal is input and a period (nT +) times (n + 1/2) times the clock period (T).
T / 2), a first delay circuit that delays and outputs with a delay time equal to T / 2), an exclusive OR operation of the signal output from the first delay circuit and the digital signal, and the OR operation An exclusive OR circuit that simultaneously generates a positive-phase output signal and a negative-phase output signal of the above, and an inverted OR circuit in which the positive-phase output signal of the exclusive OR circuit is input to one input terminal. , The output signal of the inverting OR circuit is delayed by a delay time equal to a period (nT + T / 2), which is (n + 1/2) times the clock period (T), and is delayed to the other input terminal of the inverting OR circuit. When the output signal of the opposite phase of the exclusive OR circuit is input to the second delay circuit to be supplied and one of the input terminals, the inversion AND circuit and the output signal of the inversion AND circuit are supplied to the clock cycle ( (N + 1/2) times the period (nT +)
T / 2) with a delay time equal to T / 2), and supplying the other input terminal of the inverting AND circuit to the other input terminal of the inverting AND circuit. The output signal is a two-phase clock signal.

[0014]

According to the present invention having such a configuration, the inverting OR circuit and the second delay circuit have a cycle (nT + T / T) according to the logic of the positive phase output signal of the exclusive OR circuit.
Since it becomes a feedback oscillation state in which the oscillating operation is performed in 2), the output of the inverting logical sum circuit becomes a clock signal synchronized with the period (T), while the inverting logical product circuit and the third delay circuit are:
Since the feedback oscillation state in which the oscillation operation is performed in the cycle (nT + T / 2) is performed according to the logic of the output signal of the opposite phase of the exclusive OR circuit, the output of the inversion OR circuit is a clock synchronized with the cycle (T). It is a signal and has a phase opposite to the output of the inverting logical sum circuit. Therefore, two-phase clock signals having mutually opposite phases can be obtained. Further, the delay time of the first to third delay circuits is set to be equal to the cycle (nT + T / 2) times (n + 1/2) times the predetermined clock cycle. The capacitor for setting the constant can be made small in capacity, and a small clock signal extraction circuit can be realized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, a circuit configuration will be described with reference to FIG. 1. A first stage circuit I including a first delay circuit 6 and an exclusive OR gate 7, an inverting OR gate (hereinafter, referred to as NOR gate) 8 and a second Delay circuit 9, an inverted AND gate (hereinafter referred to as a NAND gate) 10 and a third delay circuit 11
It has a second-stage circuit I composed of

In the first stage circuit I, one input terminal P _a of the exclusive OR gate 7 is connected to an input terminal P _in to which a digital signal S _in transferred from a transmission line of a digital communication system or the like is applied. Is directly connected to the other input terminal P _b
Is applied with the delayed digital signal S _in via the first delay circuit 6.

Here, the digital signal S _in is a NRZ (non-return zero) encoded digital signal in synchronization with a predetermined clock cycle T. Furthermore, the first delay circuit 6
Is set to a delay time equal to a period (2n + 1) T / 2 that is (n + 1/2) times the predetermined clock period T. However, the coefficient n is a natural number including 0, and therefore T / 2, 3T / 2, 5T / 2, ..., (2n +
1) The delay time is set to either T / 2.

The exclusive OR gate 7 has two terminals P _a.
Exclusive OR is calculated to generate an output signal of the positive phase of the calculation result to one output terminal P _c, the other output terminal an output signal of the positive phase of the operation result of the signal input to P _b P
occurs in _f .

In the latter stage circuit II, the NOR gate 8
One of the input terminals is connected to the output terminal P _c , and
The other input terminal connected to the output terminal P _e of the second delay circuit 9, further, the output terminal P _d of the NOR gate 8 is connected to the input terminal of the second delay circuit 9. On the other hand, NAN
One input terminal of the D gate 10 is connected to the output terminal P _f , the other input terminal is connected to the output terminal P _h of the third delay circuit 11, and the output terminal P _g of the NAND gate 10 is further connected. It is connected to the input terminal of the third delay circuit 11. Then, the extracted clock signal S _ck and the clock signal S _ckb having the opposite phase _thereof are _generated at the output terminals P _d and P _f , respectively.

Here, the second and third delay circuits 9 and 11
Both have the same delay time as that of the first delay circuit 6. That is, as described above, the predetermined clock cycle T
To (n + 1/2) times the period (2n + 1) T / 2
Is set to a delay time equal to.

The first to third delay circuits 6, 9, 1
1 has a time constant circuit that determines the time constant by the integration action of a capacitor and sets the delay time from the time constant. Furthermore, when the reset signal RS from the outside is applied, the second and third delay circuits 9 and 11 initialize the integration operation by discharging the charge accumulated in the internal capacitor, and output the outputs. Terminal P _e
It also has a built-in reset circuit that simultaneously resets the outputs of P and P _h to logic "0".

The operation of this embodiment will be described below with reference to the timing chart of FIG. The waveform of each shown in FIG. 2 shows a waveform of the signal appearing at terminal P _a to P _g of each in FIG. Also, the first to third delay circuits 6, 9, 11
The case where the delay time of is set to T / 2 will be described.

First, by applying the reset signal RS to the second and third delay circuits 9 and 11, the terminals P _e and P _e
After the signal level of _h is set to logic “0”, the digital signal S _in is ready for input.

Next, as shown in FIG. 2, for example, the signal S _in
Is NRZ-coded in synchronization with the cycle T.
Assuming that the digital signal is 10010 ″, the signal input from the first delay circuit 6 to the input terminal P _b of the exclusive OR gate 7 is the same as the signal S _in delayed by T / 2. As a result, the output terminal P of the exclusive OR gate 7
_{In c} , as shown in the figure, "1" synchronized with the cycle of T / 2
A positive phase signal of "0101010001000100010101" is generated, and at the other output terminal P _f , as shown in the figure, "01010101110111" which is in synchronization with the cycle of T / 2 and has a phase opposite to the signal of the output terminal P _c.
011101010 "reverse phase signal is generated. It should be noted that these terminals P _b, the signal of P _f is over a period logic level is more than the period T of the signal S _in" 1
When it is continuous like "1 ..." or "00 ...", the waveform has a missing tooth state, so that the signal does not yet faithfully reproduce the clock cycle T.

In the circuit composed of the NOR gate 9 and the second delay circuit 9, the positive phase signal generated at the terminal P _c is synchronized with the cycle T / 2 as shown in the period τ _a in the figure. When the logic is alternately inverted as in “101010”, the signal S _ck generated at the terminal P _d is the inverted signal of the normal phase signal generated at the terminal P _c regardless of the logic level of the signal at the terminal P _e. Becomes That is, the signal S _ck is “010101”
The signals are logically inverted alternately. Therefore,
In such a period τ _a , the signal S _ck becomes a signal that faithfully represents the clock cycle T.

On the other hand, as indicated by the period τ _b in the figure, the positive phase signal generated at the terminal P _c is “1000100010.
When the logic "0" continues for a period equal to or longer than the cycle T, such as 001 ", the NOR gate 8 causes the signal appearing at the terminal P _e of the second delay circuit 9 after the delay time T / 2 and the terminal P _c. Since the in-phase OR operation is performed with the positive phase signal of, the signal appearing at the terminal P _d is "0101010101010".
As described above, the signals are logically inverted alternately in synchronization with the cycle T / 2. That is, even if the logic of the positive phase signal generated at the terminal P _c is the same logic level continuously in the period of the period T or more, the signal S
_ck is a signal that faithfully represents the clock cycle T.

As described above, since the circuit including the NOR gate 8 and the second delay circuit 9 is a kind of feedback oscillation circuit which oscillates in the cycle T / 2 by having the feedback loop, it has a predetermined value. A clock signal _Sck that is faithfully synchronized with the clock cycle T is formed.

On the other hand, in the circuit comprising a NAND gate 10 from the third delay circuit 11 is phase-inverted signal generated at the terminal P _f is as shown in the period tau _a in the drawing, the period T /
When the logic is alternately inverted like "010101" in synchronization with 2, the signal S _ckb generated at the terminal P _g is the reverse generated at the terminal P _f regardless of the logic level of the signal at the terminal P _h. It becomes an inverted signal of the phase signal. That is, the signal S _ckb becomes a signal which is logically inverted alternately like “ ₁₀₁₀₁₀ ”. Therefore, in such a period τ _a , the signal S _ckb becomes a signal that faithfully represents the clock cycle T.

On the other hand, as indicated by the period τ _b in the figure, the negative phase signal generated at the terminal P _f is "0111011101".
When the 1 "consecutive" logic over a period of more than the period T as "110, NAND gate 10, after a delay time T / 2 appearing at terminal P _h of the third delay circuit 11 the signal and the terminal P _f Since an inverted logical product operation is performed on the opposite phase signal of the above, the signal appearing at the terminal P _g is "10101010101.
The signal becomes a signal which is alternately inverted in synchronism with the cycle T / 2, such as 01 ". That is, even _if the logic of the negative phase signal generated at the terminal P _f is the cycle T or more and the same logic level continues. ,
The signal S _ckb is a signal that faithfully represents the clock cycle T.

As described above, since the circuit including the NAND gate 10 and the third delay circuit 11 is a kind of feedback oscillation circuit which oscillates in the cycle T / 2 by having the feedback loop, it has a predetermined value. A clock signal S _ckb that is faithfully synchronized with the clock cycle T is formed.

As shown in the figure, the clock signal S _ck generated at the terminal P _d and the clock signal S _ckb generated at the terminal P _g are synchronized with the cycle T and have logical levels opposite to each other. It has a relationship of two-phase clock signals.

As described above, according to this embodiment, the delay time of the first to third delay elements 6, 9 and 11 can be set to 1/2 of the clock cycle T, so that this delay time is set. A small capacitor can be used to do this. Therefore, a small clock signal extraction circuit can be realized, which is particularly suitable for IC and LSI. Furthermore, two-phase clock signals S that are in opposite phase relation to each other
_{Since ck} and S _ckb are generated at the same time, they are excellent in versatility for various electronic devices.

[0033]

As described above, according to the present invention, the clock for extracting the clock signal synchronized with the clock cycle (T) from the digital signal NRZ encoded in synchronization with the predetermined clock cycle (T). A first delay circuit that outputs the digital signal after being delayed by a delay time equal to a period (nT + T / 2) that is (n + 1/2) times the clock period (T) in the signal extraction circuit; An exclusive OR circuit for performing an exclusive OR operation of the signal output from the delay circuit 1 and the digital signal to simultaneously generate a positive-phase output signal and a negative-phase output signal of the OR operation. When the positive-phase output signal of the exclusive OR circuit is input to one of the input terminals, the output signal of the inversion OR circuit and the inversion OR circuit is (n + 1 /) of the clock cycle (T).
2) A second delay circuit which is delayed by a delay time equal to twice the cycle (nT + T / 2) and is supplied to the other input terminal of the inverting OR circuit, and the exclusive OR circuit is connected to one input terminal. When the output signal of the opposite phase of is input, the inverting AND circuit,
The output signal of the inverting AND circuit is set to the clock cycle (T).
A third delay circuit which supplies a signal to the other input terminal of the inverting AND circuit by delaying it with a delay time equal to (n + 1/2) times the cycle (nT + T / 2) Since the output signal of the circuit and the output signal of the inversion AND circuit are two-phase clock signals, this delay time (nT
A small capacitor can be used to set + T / 2). Therefore, a small clock signal extraction circuit can be realized, which is particularly suitable for IC and LSI. Further, since two-phase clock signals having mutually opposite phases are generated at the same time, it is possible to provide a clock signal extraction circuit excellent in versatility for various electronic devices.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a clock signal extraction circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a circuit diagram showing a configuration of a conventional example of a clock signal extraction circuit.

FIG. 4 is a timing chart for explaining the operation of the conventional example.

FIG. 5 is a circuit diagram showing the configuration of another conventional example of the clock signal extraction circuit.

FIG. 6 is a timing chart for explaining the operation of another conventional example.

[Explanation of symbols]

6, 9, 11 ... Delay circuit, 7 ... Exclusive OR gate, 8
... Inversion logical sum gate, 10 ... Inversion logical product gate.

Claims (1)

[Claims] 1. N in synchronization with a predetermined clock period (T)
In a clock signal extraction circuit for extracting a clock signal synchronized with the clock cycle (T) from an RZ-encoded digital signal, the digital signal is input and the clock cycle (T)
(N + 1/2) times the cycle (nT + T / 2) of the first delay circuit that delays and outputs the delay signal, and the exclusive logic of the signal output from the first delay circuit and the digital signal. An exclusive-OR circuit that performs a sum operation to simultaneously generate a positive-phase output signal and a negative-phase output signal of the logical-sum operation, and a positive-phase output of the exclusive-OR circuit at one input terminal An inversion OR circuit to which a signal is input, and an output signal of the inversion OR circuit is the clock cycle (T).
A second delay circuit which is delayed by a delay time equal to (n + 1/2) times (nT + T / 2) times and is supplied to the other input terminal of the inverting OR circuit, When the output signal of the opposite phase of the logical OR circuit is input, the inverted AND circuit outputs the output signal of the inverted AND circuit to the clock cycle (T).
(N + 1/2) times the cycle (nT + T / 2) of the delay time, and supplies the delayed signal to the other input terminal of the inverting AND circuit. A clock signal extraction circuit, wherein the output signal of the circuit and the output signal of the NAND circuit are two-phase clock signals.