JP3521275B2 - Phase matching device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission apparatus for performing internal processing in parallel by a plurality of large-scale integrated circuits (LSIs). The present invention relates to a phase matching device for correcting a phase difference. 2. Description of the Related Art Conventionally, when synchronizing parallel external outputs from a plurality of identical LSIs, a plurality of LSIs having a retiming function and an internal counter are combined with a voltage controlled oscillator (VCO) to form a single LSI. A timing pulse is supplied from one LSI to another LSI to synchronize it. In this device, one LS is transmitted from a VCO.
A clock is supplied to I, and a read timing pulse is generated by an internal counter. This timing pulse is also supplied to the retiming unit of another LSI to synchronize the parallel external output. FIG. 3 is a block diagram showing a configuration of a conventional phase matching device. FIG. 4 is a time chart for explaining the operation of the phase matching device of FIG. 3, and the signs of the signals in the figure match the signs of the signals in FIG.
The phase matching device shown in FIG. 3 combines two LSIs and one VCO, generates a timing pulse for internal processing in one LSI, supplies the timing pulse to the other LSI, and synchronizes an external output. . As shown in FIG. 3, a first circuit device (LS
I # 1) 50 is the first retiming block (ES
1) 51 and second retiming block (ES2) 5
2, an internal counter (CTR) 53, and a phase comparison block (PC) 54. Similarly, the second circuit device (LSI # 2) 7
0 is also the first retiming block (ES1) 51,
Second retiming block (ES2) 52, internal counter (CTR) 53, and phase comparison block (PC) 5
4 is provided. Referring also to FIG. 4, ES1 51 includes frame pulse (FP) 56 and data (DATA) from outside.
57, a clock (CLK) is input, retiming is performed, and a timing pulse 6 generated by the internal counter 53
5 outputs FP59 and DATA60 to the outside. However, the timing pulse of LSI # 2 · 70 is not generated internally, and the timing pulse from LSI # 1 · 50 is
5 is received. [0008] The ES2 52 includes an internal processing FP 61,
Clock 62 is input to perform timing, and FP after retiming is applied by clock 63 supplied from VCO 55.
64 is sent to the internal counter 53. However, LSI # 2
ES70 of ES70 is unused. The CTR 53 includes a retiming block 52
It is controlled by the input FP 64 and generates a timing pulse 65 necessary for internal processing of the LSI. (LS
The CTR 53 of I # 2 • 70 is unused. The PC 54 receives a clock 6 input from the outside.
2 and the phase comparison result 66 of the clock 63 input from the VCO 55 is sent to the VCO 55. The VCO 55 calculates the phase comparison result 66 based on the
The phase of the output clock 63 is adjusted. However, LSI # 2
PC is unused. However, in the method according to the prior art, a timing pulse generated by an internal counter of one LSI is supplied to another LSI. When this timing pulse is supplied to the outside of the LSI, a delay occurs because it passes through a gate such as a buffer. In order to correct this delay and prevent a phase difference from occurring in the output of each LSI, a circuit such as providing a delay adjustment circuit becomes complicated. Also,
To set the delay automatically by hardware, a strict delay calculation is required, and the design is difficult. Therefore, a technical problem of the present invention is to synchronize external outputs of an LSI and eliminate a phase difference between the outputs so that a complicated delay adjustment circuit and strict delay calculation are not required, and a phase matching that can be easily designed. It is to provide a device. According to the present invention, there is provided a voltage controlled oscillator (VCO) and a plurality of circuit devices connected to the voltage controlled oscillator (VCO), wherein the circuit device inputs data from outside. A first retiming block for performing retiming and outputting to the outside, a second retiming block for performing retiming of an internal processing clock and a frame pulse (FP), and a clock and FP after retiming. ,
In a phase matching device including an internal counter for generating an internal processing timing pulse in the circuit device and a phase comparison block for adjusting the phase of the output of the VCO, each output phase of the circuit device is compared and the output is compared. A phase matching device comprising a phase matching block for correcting the phase to eliminate the phase difference is obtained. According to the present invention, in the phase matching device, the phase matching block includes a phase difference determining means for generating a determination pulse when the phases of the respective FP outputs in the circuit device do not match. A clock supply stopping means for generating a control signal for stopping a VCO clock supplied to one of the circuit devices in accordance with the determination pulse;
And a VCO clock supply means for stopping the supply of the CO clock. Further, according to the present invention, in the phase matching device, the phase difference judging means includes a knot circuit connected to an FP output terminal of one of the circuit devices and another of the circuit devices. And an OR circuit that receives one of the FP output terminals and the output terminal of the knot circuit as inputs, and the clock supply means includes a first terminal having a D terminal connected to the output terminal of the OR circuit. A D terminal is connected to a flip-flop circuit and an FP output terminal of one of the circuit devices, and the first flip-flop circuit has an R terminal and an S terminal.
A second flip-flop circuit having terminals connected to each other; and a second flip-flop circuit having an S input terminal connected to the Q terminal of the first flip-flop circuit and an R input terminal connected to the Q terminal of the second flip-flop circuit. And the VCO clock supply means outputs the output from the Q terminal of the third flip-flop circuit and the VC
The clock from O55 is used as an input terminal, an OR operation is performed based on these inputs, and as a result, the VCO
And a logical sum circuit that outputs a clock. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing functional blocks of a phase matching device according to an embodiment of the present invention. FIG. 2 is a time chart for explaining the operation of the phase matching device of FIG. Referring to FIG. 1, the phase matching device includes a first circuit device (LSI # 1) 50, a second circuit device (LSI # 2) 70, a VCO 55, and a phase matching block 10. ing. The LSI # 1 · 50 includes a first retiming block (ES1) 51, a second retiming block (ES2) 52, an internal counter (CTR) 53,
A phase comparison block (PC) 54. In LSI # 1 · 50, ES1 · 51
Represents a frame pulse (FP) 56 and data (DAT
A) 57 and a clock (CLK) 58 are input, retiming is performed, and the clock 6 supplied from the VCO 55 is input.
3 to output FP60 and DATA59 to the outside.
The ES 2 52 receives the internal processing FP 61 and the clock 62, performs retiming, and uses the clock 63 supplied from the VCO 55 to output the FP 6 after retiming.
4 to the CTR 53. Also, CTR53 is ES
Load is performed by the FP 64 input from 2.52, and a timing pulse 65 necessary for internal processing of the LSI is generated. Further, the PC 54 has a clock 62 input from the outside,
The phase comparison result 66 with the clock 63 input from the VCO 55 is sent to the VCO 55. The VCO 55 adjusts the phase of the output clock 63 based on the result 66 of the phase comparison. The LSI # 2 70 is the first retiming block (ES1) 51 similarly to the LSI # 1 50.
, A second retiming block (ES2) 52, an internal counter (CTR) 53, and a phase comparison block (P
C) 54. In LSI # 2 70, ES 1 51
Inputs FP56, DATA57, and CLK58, performs retiming, and externally outputs FP71, DATA7.
2 is output. ES2 · 52 is an internal processing FP.
61, a clock 62 is input, retiming is performed, and the FP64 after retiming is sent to the CTR 53. Also, the CTR 53 is the FP64 input from the ES2 52.
To generate a timing pulse 65 necessary for the internal processing of the LSI. Further, the PC 54 is connected to the LSI # 2
・ 70 is unused. The phase matching block 10 includes a knot circuit (inverter) 1, a logical OR circuit 2, a logical OR circuit 3,
First to third flip-flop circuits 6 to 8 are provided. The knot circuit 1 inverts the polarity of the FP 71. The OR circuit 2 outputs the determination pulse 12 only when the phases of the output 11 from the FP 60 and the knot circuit match.
Occurs. The output terminal of the OR circuit 2 is connected to the D terminal of the first to third flip-flop circuits 6. The first and second flip-flop circuits 6 and 7 are provided with S
The terminal and the R terminal are connected to each other. The FP60 is input to the D terminal of the second flip-flop circuit 7. Outputs 13 and 14 from the Q terminals of the first and second flip-flop circuits 6 and 7 are input to the S terminal and the R terminal of the third flip-flop circuit 8, respectively.
The clock 63 from the VCO 55 is input to the C terminals of the first and second flip-flop circuits 6 and 7. The third flip-flop circuit 8 has the C terminal and the D terminal short-circuited and grounded, and outputs the control signal 5 from the Q terminal. The control signal 5 and the clock 63 are input to the OR circuit 3, and while the control signal 5 is being output, the output of the output VCO clock 4 is stopped. Next, the operation of the phase matching block 10 will be described with reference to FIG. 1 and further to FIG. As shown in FIGS. 1 and 2, in the phase matching block 10, the LSI # 2 70 and the LSI # 1
・ Input FP60, 71 from 50. Where FP
When the phases of 60 and 71 do not match, for example, in the upper diagram of FIG. 2, the phase of FP71 is advanced than that of FP60, and in the lower diagram of FIG. 2, the phase of FP71 is higher than that of FP60. When it is late, a determination pulse 12 is generated in the output from the OR circuit 2 as the phase difference determination means, and the first flip-flop circuit 6 as the clock supply stop means is output.
, A control signal 5 for stopping and controlling the VCO clock 4 is generated, and the control signal 5 is input to the OR circuit 3 which is the VCO clock supply means and supplied to the LSI # 2 ・ 70.
By stopping the CO clock 4 by the phase difference between FP60 and FP71, the phases are matched. On the other hand, if the phases of the FPs 60 and 71 match, the control signal 5 is not output from the third flip-flop 8 and the VCO The clock 4 is supplied without stopping. As described above, in the present invention, in order to synchronize the external output of the LSI and eliminate the output phase difference, a complicated delay adjustment circuit and strict delay calculation are not required. A phase matching device that can be easily designed can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing functional blocks of a phase matching device according to an embodiment of the present invention. FIG. 2 is a time chart for explaining the operation of the phase matching device of FIG. 1; FIG. 3 is a diagram showing functional blocks showing an example of a conventional phase matching device. FIG. 4 is a time chart for explaining the operation of the phase matching device of FIG. 3; [Description of Signs] 1 knot circuit 2 OR circuit 3 OR circuit 4 VCO clock 5 Control signals 6, 7, 8 First to third flip-flop circuits 10 Phase matching block 12 Judgment pulse 50 First circuit device (LSI # 1) 51 First retiming block (ES1) 52 Second retiming block (ES2) 53 Internal counter (CTR) 54 Phase comparison block (PC) 55 Voltage controlled oscillator (VCO) 56, 60, 61, 64, 71 frame pulse (F
P) 57, 59, 72 Data (DATA) 58, 62, 63 Clock (CLK) 65 Timing pulse 66 Phase comparison result 70 Second circuit device (LSI # 2)

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-224962 (JP, A) JP-A-3-149931 (JP, A) JP-A-5-292077 (JP, A) JP-A-7- 46229 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 7/00 G06F 1/12

Claims (1)

(57) [Claims] [Claim 1] Data input from the outside is read
This data is based on an external clock based on the frame pulse.
Data and retiming to the internal clock
Output data and output frame pulse
And the internal clock of the circuit device is shared.
Each of the circuits supplied from one internal clock generator
Corrects the phase difference of the output frame pulse output from the device
In the phase matching device, the circuit device performs retiming of the internal clock.
First retiming for outputting retiming internal clock
And the output of the first retiming block.
Output retiming pulse with force as load signal
Read out the retiming pulse
Output the output data as a
Second Rita for Determining Output Timing of Frame Pulse
An imming block, and one of the circuit devices is previously set as a phase reference, and
The output frame pulse of the circuit device to be
Detects the phase difference from the output frame pulse, and
A first filter of the circuit device for the device by the phase difference
The phase matching block that stops the output of the
A phase matching device comprising: