JP3011047B2 - Phase comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator, and more particularly, to a circuit for detecting a phase difference between a plurality of digital clock signals, in particular, a PLL (Phase Locked Loop) circuit. , TV and other audio equipment,
The present invention relates to a phase comparison circuit suitable for use in a frequency synthesizer, a communication device, and the like.

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 3 has been known as a phase comparison circuit. This phase comparison circuit includes a knot circuit 30, a delay circuit 32, an AND circuit 34, and a D (Delay) flip-flop 36, and detects a phase difference between clock signals input to input terminals 38 and 40. Detected and a pulse signal corresponding to the phase difference is output from the output terminal 42.

That is, the input terminal 38 is connected to the input terminal 38 shown in FIG.
When the clock signal 80 shown in FIG. 3 is input, the delay circuit 32 outputs a clock signal 84 shown in (c), and the AND circuit 34 outputs a clock signal 86 shown in (d). It has become. The clock signal 80 is input to the set terminal of the flip-flop 36, and the flip-flop 36 outputs the clock signal 8
6, a clock signal 88 as shown in FIG. On the other hand, a clock signal 82 as shown in FIG. 3B is input to the input terminal 40, and the output of the clock signal 88 is inverted in response to the rise of the clock signal 82. Therefore, a signal that is “1” is output from the output terminal 42 only between the rising of the clock signal 80 input to the input terminal 38 and the rising of the clock signal 82 input to the input terminal 40, The clock signal 88 is output as a signal indicating the phase difference between the clock signal 80 and the clock signal 82. Incidentally, as related to this kind of technology, Japanese Patent Application Laid-Open Nos. 2-145020, 4-207631, 63-171005, and
Publication.

[0004]

However, in the prior art,
Is the rise of clock signal 80 and clock signal 82
When the timing of approaching, it becomes impossible to operate
There is a problem. That is, the output from the AND circuit 34
Clock signal 86 rises clock signal 80
The pulse width is mainly slow.
It is determined by the delay amount of the extension circuit 32. Clock signal pal
The narrower the width, the wider the dynamic range of the phase comparison operation
But the flip-flop 36 can be set reliably.
Is required to have a sufficiently large time span
Therefore, the pulse width cannot be made infinitely narrow. others
Therefore, the period when the logic of the clock signal 86 is “1” is
When the signal overlaps the rising edge of the clock signal 82,
Timing t₁₁From timing t ₁₂As shown in the
The flip-flop 36 is output at the rising edge of the clock signal 82.
Power cannot be inverted, resulting in a clock signal
The logic of 88 is fixed to “1” and the appropriate phase comparison result
Cannot output.

In a conventional phase comparison circuit, digital L
It is difficult to use SI (Large Scale Integrated Circuit). That is, as the delay circuit 32, a simple delay line, an integrating circuit using a resistor and a capacitor, or the like is used.
It is difficult to incorporate into SI. Note that the delay circuit 32 can be configured by connecting several stages of gate circuits.
Since the delay time of the internal gate is short and the variation is large, it is difficult to obtain an appropriate delay time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase comparison circuit capable of performing a reliable phase comparison even when rising of a pair of input pulse signals approaches.

[0007]

According to the first aspect of the present invention, there is provided (a) a setting pulse signal in response to a first pulse signal when the first pulse signal is input to a first input terminal. a first pulse generating means for outputting alternately from a pair of output terminals, from (b) a first pulse generating means receives the respective signals from the one output terminal and a second input terminal of the first pulse generating means The first set signal is output by the set pulse signal of the second and the second input terminal input from the second input terminal on condition that the input of the set pulse signal is released.
(C) receiving a signal from the other output terminal and the second input terminal of the first pulse generating means, respectively, to invert the first set signal in response to the first set signal; The second set signal is output by the set pulse signal from the pulse generating means of the above, and the second set signal is responded to the second pulse signal inputted from the second input terminal on condition that the input of the set pulse signal is released. A third pulse generating means for inverting the second set signal, and (d) generating a pulse signal in accordance with a logical product of an output signal of the second pulse generating means and an output signal of the third pulse generating means. The phase comparison circuit is provided with an AND circuit for outputting.

[0008]

[0009]

[0010] That is, in the first aspect of the present invention, the first pulse generating means each time the first pulse signal is input to the first pulse generating means and second pulse generating means third pulse generating means The second pulse generating means and the third pulse generating means are set alternately, and the setting pulse signal is input to the second pulse generating means or the third pulse generating means. When not done,
When the second pulse signal is input to the second pulse generator or the third pulse generator, the second pulse generator or the third pulse generator is reset, and the output signal of the second pulse generator is output. A pulse signal according to the logical product of the output of the third pulse generating means and the output signal of the third pulse generating means is output from the logical product means.

According to the second aspect of the present invention, (a) when the first pulse signal is input to the first input terminal, the set pulse signal is output to the pair of output terminals in response to the rise of the first pulse signal. A first pulse generating means for outputting alternately from a terminal; and (b) a setting pulse from the first pulse generating means which receives signals from one output terminal and a second input terminal of the first pulse generating means. The first set signal is output in response to the rising of the second pulse signal input from the second input terminal on condition that the input of the setting pulse signal is released by the signal. (C) receiving signals from the other output terminal and the second input terminal of the first pulse generating means, respectively, and applying a setting pulse signal from the first pulse generating means. 2 A third signal for inverting the second set signal in response to a rising edge of the second pulse signal input from the second input terminal on condition that the input of the set pulse signal is cancelled. Pulse generating means;
(D) The phase comparison circuit is provided with logical product means for outputting a pulse signal according to the logical product of the output signal of the second pulse generating means and the output signal of the third pulse generating means.

That is, according to the second aspect of the present invention, each time the first pulse signal is input to the first pulse generating means,
In response to the rising edge of the first pulse signal, the first pulse generating means alternately outputs a setting pulse signal to the second pulse generating means and the third pulse generating means, and outputs the second pulse generating means and the second pulse generating means. 3 pulse generating means are set alternately,
When the setting pulse signal is not input to the second pulse generating means or the third pulse generating means, and the second pulse signal is input to the second pulse generating means or the third pulse generating means. Resetting the second pulse generating means or the third pulse generating means in response to the rise of the second pulse signal, and comparing the output signal of the second pulse generating means with the output signal of the third pulse generating means. A pulse signal according to the logical product is output from the logical product means.

According to the third aspect of the present invention, (a) the first
When the first pulse signal is input to the input terminal of
A first flip-flop that alternately outputs a setting pulse signal from a pair of output terminals in response to the pulse signal of
(B) One output terminal of the first flip-flop and the second output terminal
, The first set signal is output by the set pulse signal from the first flip-flop, and the input is made from the second input terminal on condition that the input of the set pulse signal is released. A second flip-flop that inverts the first set signal in response to the generated second pulse signal, and (c) receives signals from the other output terminal and the second input terminal of the first flip-flop, respectively. A second set signal is output by the set pulse signal from the first flip-flop and the second pulse signal input from the second input terminal is provided on condition that the input of the set pulse signal is released. A third flip-flop in response to invert the second set signal, and (d) a logical product of an output signal of the second flip-flop and an output signal of the third flip-flop. An AND circuit for outputting a pulse signal Tsu is provided to the phase comparator.

[0014] That is, in the invention of claim 3, wherein, every time the first pulse signal is input to the first flip-flop, alternately from the first flip-flop to the second flip-flop and the third flip-flop A setting pulse signal is output to alternately set the second flip-flop and the third flip-flop. When the setting pulse signal is not input to the second flip-flop or the third flip-flop, When the second pulse signal is inputted to the second flip-flop or the third flip-flop, the second flip-flop or the third flip-flop is reset, and the output signal of the second pulse generating means and the third pulse signal are inputted. The pulse signal according to the logical product with the output signal of the pulse generating means is output from the logical product means.

In the invention according to claim 4 , (a) the first
When the first pulse signal is input to the input terminal of
A first flip-flop that alternately outputs a setting pulse signal from a pair of output terminals in response to the rising edge of the pulse signal of (b), from one output terminal and the second input terminal of the first flip-flop. The first flip-flop receives the respective signals and receives the first
And the first set signal is inverted in response to the rising of the second pulse signal input from the second input terminal on condition that the input of the set pulse signal is released. 2 flip-flops and (c) the first
Receive the signals from the other output terminal and the second input terminal of the flip-flop, output the second set signal by the set pulse signal from the first flip-flop, and cancel the input of the set pulse signal. A third flip-flop for inverting the second set signal in response to a rising edge of a second pulse signal input from the second input terminal on the condition that: (d) an output signal of the second flip-flop; And a AND circuit for outputting a pulse signal according to the logical product of the output signal of the third flip-flop and the third flip-flop.

That is, in the invention described in claim 4 , every time the first pulse signal is input to the first flip-flop, the second flip-flop responds to the rising of the first pulse signal from the second flip-flop. A setting pulse signal is alternately output to the flip-flop and the third flip-flop, and the second flip-flop and the third flip-flop are alternately set. When the pulse signal is not input and the second pulse signal is input to the second flip-flop or the third flip-flop, the second flip-flop or the second flip-flop responds to the rising edge of the second pulse signal. Reset the third flip-flop,
The pulse signal according to the logical product of the output signal of the second pulse generating means and the output signal of the third pulse generating means is output from the logical product means.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.
FIG. 1 is a circuit configuration diagram of a phase comparison circuit according to one embodiment of the present invention. In FIG. 1, a D-type flip-flop 10 and a set-reset type flip-flop 1
2, 14 and an AND circuit 16, the flip-flop 10 is connected to a first input terminal 18,
The flip-flops 12 and 14 are connected to a second input terminal 20, and the AND circuit 16 is connected to an output terminal 22. The flip-flop 10 is configured as first pulse generating means, and when a clock signal (pulse signal) 50 as shown in FIG. As shown in FIGS. 2C and 2D, the set pulse signals 54 and 56 are alternately output from a pair of output terminals (Q terminal and Q bar terminal). The set pulse signals 54 and 56 are input to the set terminals of the flip-flops 12 and 14, respectively.

The flip-flop 12 outputs a pulse signal 54
In response to the set state, and outputs a pulse signal 58 as shown in FIG. The flip-flop 14 outputs a pulse signal 60 as shown in (e) in response to the pulse signal 56. Further, a clock signal (pulse signal) 52 as shown in (b) is input to the D terminal of each flip-flop 12, 14 from the second input terminal 20, and responds to the rising of the clock signal 52. The set signals 58 and 60 are inverted. That is, the flip-flop 12 constituting the second pulse generating means and the flip-flop 14 constituting the third pulse generating means are alternately set by the setting pulse signals 54 and 56, and the setting pulse signals 54 and 56 are inputted. On the condition that there is no clock signal, the clock signal 52 is reset in response to the rising edge. The set signals 58 and 60 are input to the AND circuit 16, and the AND circuit 16 outputs a pulse signal 62 according to the logical product of the set signal 58 and the set signal 60 as an output terminal 22 as logical means or logical product means. Output to

In the above configuration, when clock signals 50 and 52 as shown in FIGS. 2A and 2B are input to the input terminals 18 and 20 at timings t _{1 to} t ₁₂ , respectively.
As shown in (c) and (d), the setting pulse signals 54 and 56 are alternately output from the flip-flop 10. As a result, the flip-flops 12 and 14 are set alternately, and from the flip-flops 12 and 14,
As shown in (e) and (f), set signals 58 and 60 are output. The flip-flops 12 and 14 are reset in response to the rise of the clock signal 52 on condition that the setting pulse signals 54 and 56 are released (when the levels of the pulse signals 54 and 56 are low). Is done.

That is, among the flip-flops 12 and 14, the output of the flip-flop in the reset state is inverted with the rise of the clock signal 52.
Until the next rising time of the clock signal 50, the logic "0" is latched. During this time, the flip-flop in the set state is fixed to the set state,
The output is fixed at logic "1". Therefore, the pulse signal 62 which is the logical product of the output of the flip-flop 12 and the output of the flip-flop 14 becomes logic “0” at the rise of the clock signal 52. Then, when the clock signal 50 rises thereafter, the outputs of the flip-flops 10 are inverted, so that the flip-flop that has latched the logic “0” is set, and the output becomes the logic “1”.

On the other hand, the flip-flop in the set state is released from the set state, but latches the logic "1" until the next rise of the clock signal 52. Therefore, the pulse signal 62 which is the logical product of the output of the flip-flop 12 and the output of the flip-flop 14 becomes logical “1” at the rise of the clock signal 50. Thus, in this embodiment, from the output terminal 22,
Since the logic “1” is output at the rising edge of the clock signal 50 and the logic “0” is output at the rising edge of the clock signal 52, the rising edges of the clock signal 50 and the clock signal 52 are close to each other as shown in timing t _{11 to} t _12. Also, a reliable phase comparison can be performed.

Further, according to the present embodiment, since the phase comparison circuit is constituted only by the logic circuit, the phase comparison circuit can be easily made into a digital LSI. In the embodiment, the flip-flop 10 using a D-type flip-flop has been described, but a T flip-flop may be used instead of the flip-flop.

[0023]

As described above, according to the first aspect of the present invention, each time the first pulse signal is input to the first pulse generating means, the second pulse generating means is switched by the setting pulse signal. When the third pulse generating means is set alternately and the second pulse signal is input to the second pulse generating means or the third pulse generating means on condition that the setting pulse signal is not input, Since the second pulse generating means or the third pulse generating means is reset and a pulse signal according to the logical product of the second pulse generating means and the third pulse generating means is output from the logical product means,
Even when the rising edge of the second pulse signal and the rising edge of the second pulse signal are close to each other, a reliable phase comparison can be performed, which can contribute to the stabilization of the circuit operation and the speeding up of the phase comparison.

[0024]

According to the second aspect of the present invention, each time the first pulse signal is input to the first pulse generating means, the first pulse signal is inputted.
The second pulse generating means and the third pulse generating means are alternately set by a setting pulse signal in response to the rise of the pulse signal of the second pulse signal, and the second pulse is generated on condition that the setting pulse signal is not input. When the second pulse signal is input to the means or the third pulse generating means,
The second pulse generator or the third pulse generator is reset in response to the rise of the second pulse signal, and a pulse signal according to the logical product of the second pulse generator and the third pulse generator is generated. Since the output is made from the logical product means, a reliable phase comparison can be performed even when the rising of the first pulse signal and the rising of the second pulse signal are close to each other, and the circuit operation is stabilized and the phase comparison is speeded up. Can contribute.

According to the third aspect of the invention, every time the first pulse signal is input to the first flip-flop, the second flip-flop and the third flip-flop are set by the setting pulse signal.
Are alternately set, and when the second pulse signal is input to the second flip-flop or the third flip-flop on the condition that the setting pulse signal is not input, the second flip-flop is set. Alternatively, the third flip-flop is reset, and a pulse signal according to the logical product of the second flip-flop and the third flip-flop is output from the logical product means.
Even when the rising edge of the second pulse signal and the rising edge of the second pulse signal are close to each other, a reliable phase comparison can be performed, which can contribute to the stabilization of the circuit operation and the speeding up of the phase comparison.

According to the fourth aspect of the present invention, every time the first pulse signal is input to the first flip-flop, the second flip-flop uses the setting pulse signal in response to the rising edge of the first pulse signal. And the third flip-flop are set alternately, and when the second pulse signal is input to the second flip-flop or the third flip-flop on the condition that the setting pulse signal is not input, Resetting the second flip-flop or the third flip-flop in response to the rising edge of the second pulse signal, and outputting from the AND means a pulse signal according to the logical product of the second flip-flop and the third flip-flop Therefore, even if the rising of the first pulse signal and the rising of the second pulse signal are close to each other, a reliable phase comparison can be performed, and the circuit It can contribute to the stabilization and speed of the phase comparator of work.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a phase comparison circuit according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of each part of the circuit shown in FIG. 1;

FIG. 3 is a circuit configuration diagram showing a conventional phase comparison circuit.

FIG. 4 is a time chart for explaining the operation of each part of the circuit shown in FIG. 3;

[Explanation of symbols]

 Reference Signs List 10 D-type flip-flop 12, 14 Set-reset type flip-flop 16 AND circuit 18 First input terminal 20 Second input terminal 22 Output terminal

Claims (4)

(57) [Claims] 1. A first pulse generator for alternately outputting a setting pulse signal from a pair of output terminals in response to a first pulse signal when the first pulse signal is input to a first input terminal. Means for receiving a signal from one output terminal and a second input terminal of the first pulse generating means and outputting a first set signal in response to a setting pulse signal from the first pulse generating means; Pulse generating means for inverting the first set signal in response to a second pulse signal input from the second input terminal on condition that the input of the first set signal has been released; Receiving the signals from the other output terminal and the second input terminal of the means, outputting the second set signal by the set pulse signal from the first pulse generating means, and canceling the input of the set pulse signal; The A third pulse generating means for inverting a second set signal in response to a second pulse signal input from a second input terminal, and an output signal of the second pulse generating means and a third pulse generation Output a pulse signal according to the logical product of the output signal of the means
A phase comparison circuit comprising: a logical product unit. A first input terminal for outputting a setting pulse signal alternately from a pair of output terminals in response to a rise of the first pulse signal when the first pulse signal is input to the first input terminal; A pulse generating means, receiving a signal from one output terminal and a second input terminal of the first pulse generating means and outputting a first set signal according to a setting pulse signal from the first pulse generating means; On the condition that the input of the pulse signal is released , the rising of the second pulse signal input from the second input terminal
Second pulse generating means for inverting the first set signal in response to rising , receiving signals from the other output terminal and the second input terminal of the first pulse generating means, respectively, The second set signal is output in response to the set pulse signal , and the second pulse signal input from the second input terminal rises on the condition that the input of the set pulse signal is released.
A third pulse generating means for inverting the second set signal in response to rising , and a pulse signal according to a logical product of an output signal of the second pulse generating means and an output signal of the third pulse generating means. A phase comparison circuit, comprising: a logical product unit for outputting. 3. A first flip-flop which alternately outputs a set pulse signal from a pair of output terminals in response to the first pulse signal when the first pulse signal is input to the first input terminal.
And flip-flop, a first set of signals output by the first flip-one output terminal and the first flip-flop or <br/> et setting pulse signals of receiving a signal from the second input terminal of the flop A second flip- flop that inverts the first set signal in response to the second pulse signal input from the second input terminal on condition that the input of the setting pulse signal has been released ;
Drop a first flip-flop other output terminal and the second set outputs a second set signal by the first flip-flop or <br/> et setting pulse signal receiving respective signals from the input terminal Flip-flop that inverts the second set signal in response to the second pulse signal input from the second input terminal on condition that the input of the input pulse signal is released.
Drop and the output signal of the second flip-flop and the third flip
Phase comparison circuit, characterized by comprising an AND circuit for outputting a pulse signal in accordance with the logical product of the output signal of the drop. 4. A first pulse output from a pair of output terminals in response to a rising edge of the first pulse signal when the first pulse signal is input to the first input terminal. A flip-flop, receiving a signal from one output terminal and a second input terminal of the first flip-flop, outputting a first set signal by a set pulse signal from the first flip-flop, and outputting a set pulse signal; the second pulse signal input is inputted from the second input terminal to the condition that has been released
The second inverting the first set signal in response to the rising edge
And a second set signal is output from the other output terminal and the second input terminal of the first flip-flop and outputs a second set signal by a set pulse signal from the first flip-flop. Of the second pulse signal input from the second input terminal on condition that the input of
A third inversion of the second set signal in response to the rising edge
And a AND circuit that outputs a pulse signal according to the logical product of the output signal of the second flip-flop and the output signal of the third flip-flop.