JPH04229778A - Vertical synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE:To integrate the circuit to the system of an optional clock signal without varying the circuit scale by obtaining a delay circuit for a delay time through the frequency division of a counter so as to set the delay time in terms of a frequency division ratio of the counter. CONSTITUTION:In the vertical synchronizing signal separator circuit receiving a composite synchronizing signal and separating a vertical synchronizing signal included in the composite synchronizing signal, a storage circuit 10 latches the composite synchronizing signal by using a clock, a counter section 14 receives an output of the storage circuit 10 and the composite synchronizing signal to count a consecutive state number. A latch circuit 15 uses an output of the counter section 14 as a clock to change the state of the composite synchronizing signal and outputs the vertical synchronizing signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronization signal separation circuit for separating a vertical synchronization signal from a composite synchronization signal such as a television broadcast signal.

0002

2. Description of the Related Art Generally, a composite synchronization signal of a television broadcast signal is shown in the waveform diagram of FIG. This composite synchronization signal is composed of a horizontal synchronization signal (pulse width PW 4.8 μs), an equalization pulse (pulse width PW 2.5 μs), and a vertical synchronization signal including a cutting pulse (pulse width PW 4.4 μs). The synchronization signal interval 1H is 63.6 μs, and the equalization pulse interval is 0.5H.

Conventionally, there is a circuit shown in the circuit diagram of FIG. 9 as a circuit for separating a vertical synchronizing signal from this composite signal. This circuit inputs the input signal to the D-type flip-flops 21 to 2.
It consists of a holding circuit (R-S flip-flop 29) which is set or reset when the output level of all delay circuits becomes high level or low level. There is.

That is, a composite synchronizing signal is inputted from an input terminal 1, and D-type flip-flops 21 to 2 connected in cascade are connected to each other.
6 and the output Q of these D-type flip-flops 21 to 26
It is comprised of AND operation elements 27 and 28 which receive inputs from 0 to Q5, and an RS type flip-flop 29 that is set and reset by these AND operation elements 27 and 28.

The RS type flip-flop 29 delays the input composite synchronization signal by 1.33 μs when each of the outputs Q0 to Q5 of the D type flip-flops 21 to 26 is "1", that is, the composite synchronization signal is 7. 98μs (1.33μs
x6) is set when the state is "1", and each output Q0~Q
5 are all "0", the composite synchronization signal is "0" for 7.98 μs.
Since it is reset when the pulse width is 0, horizontal synchronizing signals (4.8 μs) with a pulse width of 7.98 μs or less and equalization pulses (2.5 μs)
μs) is removed, and only the vertical synchronizing signal is output to the RS flip-flop 29 at a predetermined timing and a predetermined pulse width.

[0006]

[Problems to be Solved by the Invention] This conventional vertical synchronization signal separation circuit requires a delay circuit for the delay time, so if the delay time of the delay circuit is reduced, the number of stages of the delay circuit increases, and the circuit configuration There was a problem that there were many. There is also the problem that the lower the frequency to be separated, the greater the number of delay circuits.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical synchronization signal separation circuit which can solve such problems and can be configured with a simple circuit.

[0008]

[Means for Solving the Problems] The present invention provides a vertical synchronization signal separation circuit that inputs a composite synchronization signal and separates and outputs a vertical synchronization signal included in the composite synchronization signal.
a memory circuit that holds the composite synchronization signal using a clock; a counter unit that inputs the output of the storage circuit and the composite synchronization signal to count the number of consecutive states; and a holding circuit that changes the state of and outputs it as the vertical synchronization signal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram of FIG. The composite synchronization signal COMPSYNC from the input terminal 1 is frequency-divided by the event counter 14 based on the number of matches with the D-type flip-flop 10, and is stored in the D-type flip-flop 15. For example, the period 1 of clock φ
．． 33 μs, the frequency division ratio of the event counter 14 is “6”,
When the values of the D-type flip-flops 10 and 15 are low level (hereinafter referred to as L), when a high level (hereinafter referred to as H) is continuously input to the composite synchronization signal, the D-type flip-flop 10 outputs the low level and composite synchronization signal. is H, the coincidence detection circuit 11 is L, the AND circuit 13 is L, the AND circuit 12 is H,
The event counter 14 is cleared to a count value of 0, and the D-type flip-flop 10 is set from L to H. After 1.33 μs, the composite synchronization signal and the D-type flip-flop 10 are both at H, and the coincidence detection circuit 11 is at H,
The AND circuit 12 becomes L, the AND circuit 13 becomes H, and the event counter 14 is incremented to a count value of "1".

Similarly, the event counter 14 is incremented every 1.33 μs, and the event counter 14 is incremented every 1.33 μs.
μs×6), the output of the event counter 14 whose count value is “6” becomes H, and the D-type flip-flop 1
5 is set from L to H. Furthermore, for pulses shorter than 7.98 μs, the event counter 14 is cleared, so the value of the D-type flip-flop 15 of the memory circuit does not change. That is, pulses of approximately 8 μs or less, such as equalization pulses, in the composite synchronization signal as shown in FIG. 8 are removed, and only the vertical synchronization signal is separated.

[0011] Also, the period of the clock φ is set to 0.67 μs,
If the frequency division ratio of the event counter 14 is set to 12, pulses of approximately 8 μs (0.67 μs×12) or less can be removed, as described above.

FIG. 3 is a block diagram of a second embodiment of the present invention, and FIG. 4 is an operational waveform diagram thereof. This embodiment uses a counter 16 and a comparator 17 instead of the event counter 14 of the first embodiment. The output signal and the input signal are subjected to an exclusive OR in an EX-OR circuit 18, and the logical product of this EX-OR output and the output of the comparator 17 by the AND circuit 17 becomes the clock for the D-type flip-flop 15. ing. In this embodiment, by making the comparator programmable,
The pulse removal width can be set freely.

FIG. 5 is a circuit diagram of a third embodiment of the present invention, and FIG. 6 is a timing diagram of FIG. This embodiment is a circuit in which D-type flip-flops 30 and 31 for synchronizing an input signal with a clock and an inverter 32 for a clock CLK are added to the first embodiment.

Digital signal A is a signal obtained by synchronizing an external digital input signal with D-type flip-flop 30, and the output of D-type flip-flop 10, which is the first latch circuit, matches digital signal A. During this period, the clock signal φ is frequency-divided by the event counter 14, and when the event counter 14 reaches a predetermined count number, it outputs H.

In synchronization with the rise of the output of the event counter 14, the D-type flip-flop 15 of the second latch circuit latches and outputs the output of the D-type flip-flop 21. For example, if the frequency division ratio of the clock φ is 1.33 μs and the frequency division ratio of the event counter 14 is 6, then the D-type flip-flop 30 is
, 15 is L, when the digital input signal continues to be H, the digital signal A becomes H in synchronization with the rising edge of the clock φ, the output of the D-type flip-flop 10 is L, and the output of the comparator circuit 11 is L, the output of the AND circuit 13 becomes L, and when the clock φ falls, the output of the AND circuit 12 becomes H, and the event counter 14 is cleared and the count value becomes 0.
becomes.

When the clock φ rises once more, the output of the D-type flip-flop 10 is set from L to H. Next, when the clock φ falls, the outputs of the digital signal A and the D-type flip-flop 10 are both H, the output of the comparison circuit 11 is H, the output of the AND circuit 12 is L, and the output of the AND circuit 13 is H, and when the clock φ rises one more time, the event counter 14 is incremented to a count value of 1.

Similarly, the event counter 14 is incremented every 1.33 μs, and the event counter 14 is incremented every 1.33 μs.
After 3 μs x 6), when the count value reaches 6, the output of the event counter 14 becomes H and the D-type flip-flop 1
5 latches the output of the D-type flip-flop 31, and the output is set from L to H. Further, for pulses shorter than 7.98 μs, the event counter 14 is cleared, so the output value of the D-type flip-flop 15 does not change. That is, pulses of approximately 8 μs or less in the digital input signal as shown in FIG. 8 are removed, and only low frequency components are separated.

[0018] Also, the period of the clock φ is set to 0.67 μs,
If the frequency division ratio of the event counter 14 is set to 12, pulses of approximately 8 μs (0.67 μs×12) or less can be removed, as described above.

FIG. 7 is a block diagram of a fourth embodiment of the present invention. In this embodiment, a circuit similar to that shown in FIG. 5 is added to a circuit similar to that shown in FIG. 3, and the pulse removal width can be freely set by making the comparator programmable.

[0020]

[Effects of the Invention] As explained above, the present invention replaces a plurality of delay circuits with counters, so the delay time can be set by the division ratio of the counter, and it can be incorporated into any clock system. It has this effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a signal waveform diagram at each part in FIG. 1.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a signal waveform diagram at each part in FIG. 3;

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

FIG. 6 is a signal waveform diagram at each part in FIG. 5;

FIG. 7 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 8 is a waveform diagram of a general composite synchronization signal.

FIG. 9 is a circuit diagram of an example of a conventional vertical synchronization signal separation circuit.

[Explanation of symbols]

1 Input terminal 2 Output terminals 10, 15, 21 to 26, 30, 31 D-type flip-flops 11, 18 Comparison circuits 12, 13, 19, 27, 28 AND circuit 14
Event counter 16 Counter 17 Comparator 29 RS type flip-flop 31 Inverter

Claims (4)

[Claims] 1. A vertical synchronization signal separation circuit that inputs a composite synchronization signal and separates and outputs a vertical synchronization signal included in the composite synchronization signal, comprising: a storage circuit that holds the composite synchronization signal using a clock; and this storage circuit. a counter section that inputs the output of the counter section and the composite synchronization signal to count the number of consecutive states; and a holding circuit that uses the output of the counter section as a clock to change the state of the composite synchronization signal and outputs it as the vertical synchronization signal. A vertical synchronization signal separation circuit comprising: 2. The vertical synchronization signal separation circuit according to claim 1, wherein the counter section is an event counter that is reset at a predetermined frequency division value. 3. The vertical synchronization signal separation circuit according to claim 1, wherein the counter section comprises a counter that counts up to a predetermined value, and a comparator that outputs a comparison output that becomes a clock when the counter reaches a predetermined value or more. . 4. A first latch circuit in which a digital input signal is latched in synchronization with a clock and outputted to a storage circuit; and an output of the first latch circuit is latched in synchronization with an inverted clock and outputted to a holding circuit. 4. The vertical synchronizing signal separating circuit according to claim 2, further comprising a supplied second latch circuit.