JPH08223447A - Synchronizing signal separator circuit - Google Patents

Abstract

PURPOSE: To separate a vertical synchronizing signal (VD) from a composite synchronizing signal (C.SYNC) without the need for analog components. CONSTITUTION: Counters 6, 8 count the number of clock signals whose width is larger than that of a horizontal synchronizing signal and smaller than that of a vertical synchronizing signal. The counter 6 counts a clock 1 when the C.SYNC 2 is at an L level. The counter 6 outputs an H signal (1) for a period of the vertical synchronizing signal, an inverter circuit 7 inverts the H signal into an L level and the inverted signal is given to a D latch 10, which outputs an L signal (6) when the C.SYNC applied to a latch terminal is at an L level, that is, for the VD period. The counter 8 is reset by the C.SYNC and counts clock signals when the C.SYNC is at an H level and provides an output of an H signal after the VD period is terminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit, and more particularly to a sync separation circuit for generating a signal for separating a vertical sync signal from a composite sync signal without using analog parts.

[0002]

2. Description of the Related Art For separating a vertical synchronizing signal from a composite synchronizing signal, for example, analog parts such as a resistor and a capacitor are connected to an integrated circuit for synchronizing separation, the composite synchronizing signal is integrated, and an integrated level is obtained. The vertical synchronization period is determined by. This utilizes the fact that the L level is long during the vertical synchronization period (when the composite synchronization signal has a negative polarity) and the integration level is high. As described above, if the sync separation circuit is configured by using a resistor and a capacitor, the volume of the circuit component becomes large. If this circuit is arranged on a printed wiring board, a large area is required, and many other circuits are required. When the circuit is composed of an integrated circuit, the large area of this portion poses a problem.

[0003]

In view of the above-mentioned problems, the present invention configures a signal for separating a vertical synchronizing signal from a composite synchronizing signal by a digital circuit using a semiconductor element or the like, and other digital circuits or the like. In addition, it is possible to reduce the cost and the circuit area by making it possible to be incorporated in an integrated circuit.

[0004]

In order to solve the above problems, the present invention counts required clocks during the L level period of a negative polarity composite synchronizing signal, and outputs the signal when the required count is exceeded. A first counter, a first latch circuit for latching and outputting the signal from the first counter with the composite synchronization signal, and counting the clock during the H level period of the composite synchronization signal, and when the count is equal to or more than the required count number And a second counter that outputs a signal to the first counter and applies the signal to the first counter to reset it.

[0005]

With the above configuration, in the sync separation circuit according to the present invention, the required clocks are counted during the L level of the composite sync signal (when the composite sync signal is negative), and the count number is vertical. L of pulse other than sync pulse
When the value is larger than the value of the level period and is within the L level period of the vertical synchronizing pulse, it is determined that the period is the vertical synchronizing period, and a signal is output. The vertical sync signal is separated using this signal.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a sync separation circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of essential parts of an embodiment of a sync separation circuit according to the present invention. In the figure, 1 is an input terminal of a clock (clk), and 2 is an input terminal of a composite negative sync signal (C.sync). An inverting circuit 3 inverts the polarity of the negative polarity composite synchronizing signal 2.
A logical sum (OR gate) circuit 4 logically sums the signal from the inverting circuit 3 and the signal from a counter 6 described later. 5 is a logical product (AND gate) circuit, which is a logical sum circuit 4
Signal and the signal from the inversion circuit 9 described later are ANDed. Reference numeral 6 denotes a counter, which is reset by the inversion input of the signal from the AND circuit 5, counts the clock 1 during the L level period of the composite synchronizing signal 2 and outputs the H level signal at the required count number. The signal from the counter 6 is applied to the EP (parallel enable) terminal and input to the OR circuit 4. 7 is an inverting circuit, which is a counter 6
Invert the polarity of the output signal of (). A counter 8 is reset by the inverting input of the composite synchronizing signal 2 and responds to the signal from the inverting circuit 7 applied to the EP terminal, counts the clock 1 during the H level of the composite synchronizing signal 2, and An H level signal is output according to the count number.
An inverting circuit 9 inverts the polarity of the output signal of the counter 8 () and applies it to the AND circuit 5. A D latch circuit 10 latches the signal from the inverting circuit 7 with the composite positive sync signal from the inverting circuit 3 and outputs the signal.

Next, the operation of the sync separation circuit according to the present invention will be described with reference to the timing chart shown in FIG. Each of the counter 6 and the counter 8 is set to the frequency of the clock 1 used in the sync separation circuit so as to count within the L level period of the pulse other than the vertical sync pulse and within the L level period of the vertical sync pulse. It is selected accordingly. This figure shows the case where 5-bit counters 6 and 8 are used and a signal (L level) is output when 32 is counted.

When the counter 6 enters the period of the vertical synchronizing signal, the level of the composite synchronizing signal 2 is "L", the output level of the inverting circuit 3 is "H", and the output of the OR circuit 4 is "H". However, since the level of the output signal of the inverting circuit 9 is "L" as will be described later, the output of the AND circuit circuit 5 becomes "L" and the counter 6 starts counting the clock 1. Since the width of the vertical synchronizing signal is 32 clocks or more during the period of the vertical synchronizing signal, the output signal of the counter 6 becomes the “H” level, the polarity of the signal is inverted by the inverting circuit 7, and the “L” level. Signal, and D
When the level of the composite sync signal of the positive polarity, which is input to the D terminal of the latch 10 and input to the latch terminal of the D latch 10, is “H”, the signal of “L” level is output.
In addition, except for the period of the vertical synchronizing signal, L of the composite synchronizing signal
Since the level width is 32 clocks or less, the output signal of the counter 6 is at "L" level, and the signal becomes "H" level to latch the D latch 10.

On the other hand, the composite synchronizing signal 2 is inverted and input to the reset terminal of the counter 8, and the composite synchronizing signal 2
Is reset at level "L" and this level is "H"
When, the count of clock 1 is started. In the period of the vertical synchronizing signal, since the width of the cutting pulse is 32 bits or less, the level of the output signal is "L". Therefore, the output signal of the inverting circuit 9 becomes the "H" level, and the period of the vertical synchronizing signal is After that (equalization pulse period and horizontal synchronization signal period), since the width of the “H” level of the composite synchronization signal 2 is wide, the count number reaches 32, the output signal becomes the “H” level, and the inversion occurs. The output signal of the circuit 9 is "L"
Level.

This signal is input to the AND circuit 5, whereby the level of the output signal of the counter 6 becomes "L" at the end of the period of the vertical synchronizing signal after the end of the period of the vertical synchronizing signal. Moreover, since the composite synchronizing signal 2 is in the equalizing pulse period and the level is "H", and the output level of the inverting circuit 3 is "L", the output of the logical sum circuit 4 becomes "L" level. An output signal is output from the AND circuit 5, and the counter 6 is reset. After that, the width of the “L” level of the composite sync signal is maintained until the next vertical sync signal period.
Since it is 32 bits or less, the output of the counter 6 becomes "L" level during this period. As a result, the D-latch 10 outputs an "L" level signal only during the period of the vertical synchronizing signal, so that the vertical synchronizing signal can be separated from the composite synchronizing signal by using this signal.

[0011]

As described above, according to the sync separation circuit of the present invention, the number of clocks in the period of the L level of the composite sync signal (when the composite sync signal has a negative polarity) is a portion other than the vertical sync signal. If it is more and within the width of the vertical synchronizing signal, it is to determine that it is the period of the vertical synchronizing signal, and since analog parts such as a capacitor are not required, it can be incorporated in an integrated circuit together with other circuits. Since it is not necessary to provide an integrated circuit dedicated to synchronization separation, the cost can be reduced and the circuit area can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of an embodiment of a sync separation circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the sync separation circuit according to the present invention.

[Explanation of symbols]

 1 clock 2 composite sync signal 3, 7, 9 inverting circuit 4 logical sum circuit (OR gate) 5 logical product circuit (AND gate) 6, 8 counter 10 D latch

Claims (3)

[Claims] 1. A first counter which counts a required clock during a period of an L level of a negative-polarity composite synchronizing signal and outputs a signal when the count is equal to or more than the required count, and a signal from the first counter is used as the composite synchronization. The first to latch and output with a signal
Synchronous separation including a latch circuit and a second counter which counts the clock during the H level period of the composite synchronizing signal, outputs a signal when the count is equal to or more than a required count, and applies the signal to the first counter to reset the clock. circuit. 2. A first inverting circuit for inverting the polarity of a negative polarity composite synchronizing signal, a logical sum circuit for computing the signal from the first inverting circuit, and a logical product circuit for computing the signal from the logical sum circuit. A third counter, which counts a required clock, outputs an H level signal when the count is equal to or more than the required count, applies the signal to the OR circuit, and is reset by a signal from the AND circuit; A second inverting circuit that inverts the output signal of the counter, a second latch circuit that latches and outputs a signal from the second inverting circuit with the composite synchronizing signal from the first inverting circuit, and is reset with the composite synchronizing signal. , A fourth counter which counts the clock in response to a signal from the second inverting circuit and outputs an H-level signal when the number of counts is greater than or equal to a required count, and inverts the polarities of the output signals of the fourth counter, The above A synchronization separation circuit including a third inverting circuit applied to the AND circuit. 3. The first counter, the second counter, and the third counter
The counter or the fourth counter counts the number of clocks that are equal to or more than the L level period of the pulse other than the vertical sync pulse of the negative polarity composite sync signal and within the L level period of the vertical sync pulse, and are reset. 3. The sync separation circuit according to claim 1 or 2, which holds the output level until it reaches the end.