JP2530025Y2 - Vertical sync signal separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) This invention relates to a vertical synchronization signal separation circuit for separating a vertical synchronization signal from a composite synchronization signal.

(Prior Art) A conventional vertical synchronizing signal separating circuit is, for example, as shown in FIG. 4, an integrating circuit composed of resistors R ₁ and R ₂ and capacitors C ₁ and C ₂ and a comparator for comparing the output of the integrating circuit with a reference voltage. be of the integral type comprising a C _P, separates the vertical synchronizing signal by a composite synchronizing signal is integrated by the integrating circuit, comparing the integrated output reference voltage.

(Problems to be solved by the invention) However, the conventional vertical synchronization signal separation circuit as described above
There is a problem that it is difficult to incorporate the resistor and the capacitor constituting the integrating circuit into the integrated circuit, and the volume and the cost are increased.

An object of the present invention is to provide a vertical synchronizing signal separation circuit suitable for integration into an integrated circuit.

(Means for Solving the Problems) A vertical synchronization signal separation circuit of the present invention is a vertical synchronization signal separation circuit for separating a vertical synchronization signal from a composite synchronization signal, and an exclusive OR having a composite synchronization signal as one input. A circuit, a timer means for generating an output by inputting a fixed number of clock pulses after being reset by the output of the exclusive OR circuit and releasing the reset, and a toggle flip-flop for performing a toggle operation by an output from the timer means Wherein the output of the toggle flip-flop is the other input of the exclusive OR circuit.

(Operation) In the present invention configured as described above, it is assumed that the vertical synchronization signal is not input and the output of the toggle flip-flop is logic "1". In this state, if the composite synchronizing signal (logic "0") is input, the reset of the timer means is released, and if the synchronizing signal ends before a fixed number of clock pulses are input, the timer is reset at the end of the synchronizing signal. You. Therefore, there is no change in the output of the toggle flip-flop.

When the synchronization signal continues until a certain number of crop pulses are input, the timer means generates an output, and the output of the toggle flip-flop is inverted to logic "0". As a result, the output of the exclusive OR circuit becomes logic “0”,
The timer is reset. This reset is continued until the composite synchronizing signal disappears, and the output of the toggle flip-flop remains at logic "0".

Next, when the composite synchronizing signal disappears, the reset of the timer means is released again, and when a certain number of clock pulses are input, the toggle flip-flop is inverted again to take the logic "1". Thus, the detection of the vertical synchronization signal is performed.

(Example) Hereinafter, this invention is demonstrated with an Example.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

The vertical synchronizing signal separation circuit according to the present embodiment includes an exclusive logic circuit 1, a timer 2 including a shift register, and a toggle flip-flop 3. The exclusive logic circuit 1 receives the composite synchronization signal and the Q output of the toggle flip-flop 3. For example, the timer 2 has a D value as shown in FIG.
A shift register of five stages consisting of flip-flops 2 ₁ to 2 _5, the serial input terminal SI is a high potential (logic "1") are added. The output of the exclusive OR circuit 1 is supplied to a reset terminal RD of the shift register. Therefore, in the timer 2, after the reset terminal RD becomes high potential (logic "1"), the _Qn output becomes high potential (logic "1") by supplying five clock pulses. Instead of the shift register, it can be constituted by a counter. The toggle flip-flop 3 is shown in FIG.
Yes constituted by exclusive-OR circuits 3 ₁ and D flip-flop 3 ₂ As shown in, Q output of the D flip-flop 3 ₂ applied as one input of the exclusive OR circuit 3 _1, Q _n outputs the timer 2 with addition to the exclusive OR circuit 3 ₁ of the other terminal (the enable terminal of the toggle flip-flop 3). When the enable terminal of the toggle flip-flop 3 is at a high potential (logic "1"), the Q output of the toggle flip-flop 3 is inverted when a clock pulse is input.

In this embodiment, the clock pulse period is sufficiently longer than 1/5 of the negative pulse width of the horizontal synchronizing portion in the composite synchronizing signal, and is sufficiently longer than 1/6 [1 / (5 + 1)] of the negative pulse width of the vertical synchronizing portion. The clock pulse has a short cycle. If the number of stages of the shift register forming the timer 2 changes, the frequency of the clock pulse also needs to be changed accordingly.

In the present embodiment configured as described above, it is assumed that the vertical synchronizing signal is not input and the Q output of the toggle flip-flop 3 is at a high potential (logic "1").

If a composite synchronizing signal is input to the exclusive OR circuit 1 and the terminal IN becomes low potential (logic "0"), the reset of the timer 2 is released. In the present embodiment, when the synchronization signal ends before the 6 (= 5 + 1) clock pulse is input, that is, in the case of the horizontal synchronization signal, the timer 2 is reset again at the end of the synchronization signal. Therefore, the Q output of the toggle flip-flop 3 does not change. 5 clock pulse is input, Q _n output of the timer 2 is a high potential (logic "1"), and the synchronization signal until the next clock pulse is input is continued, Q output of toggle flip-flop 3 is inverted Let me do.

When the Q output of the toggle flip-flop 3 is inverted and becomes a low potential (logic "0"), the output of the exclusive OR circuit 1 becomes a low potential (logic "0"), the timer 2 is reset, and the terminal IN becomes high. Timer 2 remains reset until the potential (logic "1") is reached, and the Q output of toggle flip-flop 3 is kept at a low potential (logic "0"). When the terminal IN becomes high potential (logic "1"), the timer 2 performs the shift operation again by the clock pulse, and the terminal IN keeps the high potential (logic "1") until the 6 (= 5 + 1) clock pulse is input. Then, the Q output of the toggle flip-flop 3 is again inverted,
Return to high potential (logic "1"). Thus, the vertical synchronizing signal is separated.

FIG. 3 shows the above in a timing diagram. In FIG. 3 (a), a indicates a cutting pulse, b indicates a vertical synchronizing signal, and FIG. 3 (b) indicates an exclusive OR circuit 1.
FIG. 3 (c) shows the separated vertical synchronizing signal.

In the above-described embodiment, the case where the timer 2 is configured by a shift register is illustrated, but the timer 2 may be configured by a counter.
The timer 2 only needs to generate an output by a fixed number of clock pulses after the reset operation is released.

If necessary, an output can be obtained in synchronization with the composite synchronization signal by a D flip-flop using the composite synchronization signal as a clock pulse.

(Effects of the Invention) As described above, according to the invention, the vertical synchronizing signal separation circuit can be constituted only by an exclusive OR circuit, a shift register or a counter, and a digital circuit of a toggle flip-flop. Therefore, an integrated circuit and a gate array can be formed, and there is an effect that the configuration can be made inexpensively and small.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2A is a block diagram of a shift register constituting a timer. FIG. 2 (b) is a block diagram of a torque flip-flop. FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional example. 1 and 3 ₁ ...... exclusive OR circuit, 2 ...... timer, 2 ₁ to 2 ₅
And 3 ₂ ... D flip-flop, 3.

Claims (1)

(57) [Scope of request for utility model registration] A vertical synchronizing signal separating circuit for separating a vertical synchronizing signal from a composite synchronizing signal, comprising: an exclusive OR circuit having the composite synchronizing signal as one input; A timer means for generating an output by inputting a certain number of clock pulses after the reset is released; and a toggle flip-flop for performing a toggle operation by an output from the timer means, wherein an output of the toggle flip-flop is exclusive-ORed. A vertical synchronizing signal separation circuit, which is used as the other input of the circuit.