JPH04104513A - Power-on clear circuit - Google Patents

Abstract

PURPOSE:To simultaneously start plural counters by receiving a clock pulse to be used in a circuit to be initialized and outputting a signal for initialization synchronized with this pulse from a flip flop. CONSTITUTION:A resistor 11 which has one end connected to a power source through a power terminal 13, a capacitor 12 which has one end earthed and has the other end connected to the other end of the resistor 11, and a flip flop 15 which receives the clock pulse to be used in a circuit to be initialized and outputs the signal for initialization to a power-on clear pulse output terminal 16 synchronously with the clock pulse inputted from a clock pulse input terminal 14 at the time of arrival of the voltage of the capacitor 12 for power-on at a prescribed value are provided. Thus, a power-on clear circuit is obtained which can simultaneously start plural counters.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on clear circuit used for setting an initial value when power is turned on in a logic circuit including a counter or the like.

[Conventional technology]

Conventionally, in order to determine the initial value of a counter when the power is turned on, a power supply terminal 13 and a power-on clear pulse output terminal 17 as shown in FIG.
A power-on clear circuit consisting of the following is used. The operation of this circuit is as shown in FIG. 4 when the power is turned on. In this case, since the charge on capacitor 12 is O, resistor 1
The connection point with 1 is OV. Potential a of this connection point
increases as time passes, as shown in a in FIG.

This potential a is input to the binary counter 5 via the power-on clear pulse input terminal 54 for initial setting shown in FIG.
1 clear terminal CLR.

When the potential a is less than the threshold potential V51 of the clear terminal CLR, clearing is applied, and when the potential exceeds the threshold potential, clearing is canceled as shown in a and b of FIG. Therefore, as shown in e and f of FIG. 4, the clock pulse d inputted from the clock pulse force terminal 53 starts running 1 to 1.

[Problem to be solved by the invention] In the conventional power-on clear circuit described above, is there any problem when setting the initial value for one counter?For example, as shown in FIG. Problems arise when trying to set values at the same time. That is,
In FIG. 5, whether the power-on clear pulse shown in a of FIG. 4 is input from the B-war-on clear circuit shown in FIG. 3 to the power-on clear input terminal 54, or the threshold potential of the clear terminal CLR of each counter or different (
In FIG. 4, the threshold potential of the binary counter 51 is indicated as V5□, and the threshold potential of the binary counter 52 is indicated as V52. ), there will be a shift in the start time of the counter.

In FIG. 4, t51 is the time when the binary counter 51 is cleared, and t5□ is the time when the binary counter 52 is cleared. Therefore, when these binary counters are operated by the clock pulse d, the counter outputs e, g and f, h are each 1hi=, as shown in FIG.
A deviation of l- occurs. If the clock pulse speed is increased, this slippage will further increase. As described above, the conventional power-on clear circuit has a drawback in that it is only possible to set the initial values of a plurality of counters to be the same.

An object of the present invention is to provide a power-on clear circuit that can start a plurality of counters simultaneously.

[Means to solve the problem]

The power-on clear circuit of the present invention includes a resistor whose one end is connected to a power supply, a capacitor whose one end is grounded and whose other end is connected to the other end of the resistor, and a circuit that is used for initialization. This configuration includes a flip-flop that receives the clock pulse and outputs a signal for initial setting in synchronization with the clock pulse when the voltage of the capacitor reaches a predetermined voltage when the power is turned on.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing one embodiment of the present invention, the power-on clear circuit includes a resistor 11 whose one end is connected to a power supply via a power supply terminal 13, and a resistor 11 whose one end is grounded and whose other end is connected to a power supply.
The capacitor 12 connected to the other end receives a clock pulse used in the circuit to which initial settings are to be applied, and is input from the clock pulse input terminal 14 when the voltage of the capacitor 12 reaches a predetermined voltage when the power is turned on. Black·
A flip-flop 15 is provided which outputs a signal for initial setting to a power-on clear pulse output terminal 16 in synchronization with the check pulse.

The operation will be explained below. Until the voltage is applied to the power supply terminal 13, the voltage across the capacitor 12 is 0, so the voltage at the data input terminal of the flip-flop 15 is O.
It is V. When a voltage is applied to the power supply terminal 13, the voltage of the capacitor 12 increases as shown in a in FIG. 2 by a time constant determined by the resistance and capacitance values of the resistor 11 and the capacitor 12, respectively. If the voltage of the capacitor 12 exceeds the threshold voltage of the data input terminal of the flip-flop 15 at tA after the power is turned on, 7.
January 1 The output Q of the flip-flop 15 rises to "1". This timing is determined by the edge of the clock pulse d shown in FIG. 2 applied to the terminal CK of the flip-flop 15, and the output Q of the flip-flop 15 is output immediately after the data input voltage exceeds the threshold as shown in C1 of FIG. The edge of the clock pulse d at a certain time ta is inverted.

〔Effect of the invention〕

As explained above, the present invention is configured so that a clock pulse used in a circuit to which initialization is to be applied is received, and a signal for initialization synchronized with this is outputted by a flip-flop. This has the effect that the counters can be started at the same time.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the operation of an embodiment of the present invention, and Fig. 3 is a conventional power-on clearing diagram. A configuration diagram showing the circuit. Figure 4 is a diagram to explain the operation when a conventional power-on clear pulse circuit is connected to two counters. Figure 5 is an example of a circuit using a power-on clear pulse. FIG. 11...Resistor, 12...Capacitor, 13...Power terminal, 14.53...
Clock pulse input terminal, 15...Flip-flop, 16.17...Power-on clear pulse output terminal, 51.52...Binary counter, 54... Power-on clear pulse input terminal,
55-58...Binary counter output terminal.

Claims (1)

[Claims] A resistor whose one end is connected to the power supply, a capacitor whose one end is grounded and the other end connected to the other end of the resistor, and a clock pulse used in the circuit to be initialized is received and the power supply is turned on. A power-on clear circuit comprising: a flip-flop that outputs a signal for initialization in synchronization with the clock pulse when the voltage of the capacitor reaches a predetermined voltage.