SU1185600A1 - Controlled frequency divider - Google Patents

Description

The invention relates to a pulse technique and can be used in devices of automation and computing.

The purpose of the invention is the extension -5

functionality by enabling the use of bit outputs of the pulse counter and control of the division factor. YU

FIG. 1 shows an electrical block diagram of a controlled frequency divider; in fig. 2 is an electrical functional diagram of a key (a pulse key with memorization of the control signal 15 and with the resolution of the switching of the input pulse at the output of this key); FIG. 3 - timing diagrams explaining the operation of the key. 20

The controlled frequency divider contains a pulse counter 1, the inverse outputs of the flip-flops 2-5 of each of the bits of which are connected to the first inputs of the corresponding AND-NOT elements 6-9, the second inputs of which are connected to the bus 10 of the division factor code 11 The output of which is connected to the control input of the key 12, the synchronization input of which is connected to the input bus 13, the first output - to the counting input of the first trigger 2 of the pulse counter 1, the reset inputs of the second 3 and after- unified together, an OR gate 14, control bus 15, a first, .vtoruyu and third output buses 16 - 18, respectively, com- enable input ⁴⁰ mutation on the third switch output 12 is connected to the control bus 15, the second and third outputs respectively connected to switch 12 with first and second output tires 16 and 17 ⁴⁵

and, respectively, with the first and second inputs of the element OR 14, the output of which is connected to the reset inputs of the first and second triggers 2 and 3 of the counter 1 pulses, the discharge outputs of which are connected to the third output bus 18.

The key 12 of the controlled divider: the frequencies contain the first and second elements NOT 19 and 20, respectively the first, second, third, fourth and fifth elements OR-NOT 21-25 and element AND 26, with the first input of the first element OR-NOT 21 connected to the first the output 27 of the key 12, with the output of the second element OR NOT 22, with the first input element AND 26 and with the first input of the third element OR NOT 23, the output of which is connected to the second output 28 of the key 12, with the first input of the second element OR NOT 22 and with the first input of the fourth element OR NOT 24, the second input of which is connected to the second input ohm of the first element OR-NOT 21, with the second input of the element AND 26, the third input of which is connected to the input 29 of the switching permission to the third output 30 of the key 12 connected to the output of the element AND 26, nd to the output of the fifth element OR-NOT 25, the first input which is connected to the output of the first element OR-NOT 21 and the second input of the second element OR-NOT 22, the third output of which is connected to the second input of the third element OR-NOT 23, to the output of the first element NOT 19, the input of which is connected to the input 31 of the synchronization key 12, and with the second input of the fifth element OR-NOT 25, the third entrance which is connected to a third input of the second OR-NO element 22 and to the output of the fourth OR-NO element 24, a third input coupled to.

1185600

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control input 32 key 12 and through the second element NOT 20 - with the third input of the first element

OR NOT 21.

The controlled frequency divider operates as follows.

Suppose that there is a single level on bus 15 *, the division factor of the device is K, and the output frequency is removed from bus 17.

In the initial state, the triggers 2-5 of the counter 1 are in the zero state, on the bus 10 the code of the division factor K is set, at the output of the element 11 there is a zero level, which by means of a key

12 commutes impulses from the bus

13 to the first output of the key 12. Pulses from the bus 13 are counted as counter 1. 20

At the time of the pulse on

bus 13, when the contents of counter 1 correspond to the code on bus 10, at the output of element 11 a unit level appears, which commutes the same pulse from bus 13 to bus 17. This same pulse passes through element 14 and sets counter 1 (and all device) to its original state.

Thus, the device divides the frequency of the pulses on the bus 13 by the value of the division factor equal to K, where K = 1,2,3 ... When K = 0, there are no pulses on the bus 17.

Let the bus 15 present a zero level, with the division factor of the device equal to K + 1, and the output frequency is removed from the bus 16.

40

The device in this case works as described. The differences are that the unit level at the output of element 11 only commutes the pulse from the bus 13 to the second output of the switch 12 that follows. After passing through the element 14, the pulse from the second output of the key sets the counter 1 '(and the entire device) to the initial state.

Thus, the device divides the frequency of the pulses on the bus 13 by the value of the division factor equal to K + 1, where K = 0,1,2 ...

On bus 18 in both cases there is a code corresponding to the number of pulses on bus 13, which appeared after the appearance of a pulse on tires 16 or 17.

Let us consider in more detail the operation of key 12. In the initial state, there is a zero level at the input 32, and a single one at the input 29.

Impulse 33 (Fig. 3) arrives

input 31, resulting in the output element 19 is set to zero. At all inputs of the element 22 there is a zero level, therefore, a single level is set at the output 27 (Fig. Zg). From the output of the element 25 to the input of the element 26 enters the zero level, so the output 30 will be the same level (Fig. Ze).

The next pulse 34, applied to the input 31, again passes to the output 27, Let during the action of the pulse 34 the level at the input '32 will change · from zero to single (pulse 35, fig. LC). Before the appearance of a pulse 36, the output of element 24 was a single level, and at the output of element 21, 'zero. The supply of a pulse 35 to the input 32 and the termination of the action of the pulse 37 at the output of the element 20 (Fig. 3B) during the action of the pulse 34 at the input 31 leads to the establishment of zero levels at the outputs of the elements 21 and 24. At the same time, all the inputs of the element 25 are set to zero , and at the output of this element a unit level, which, acting on the input of element 26, makes it possible to generate at output 30 a pulse 36 (Fig. Ze).

Subsequent pulses from the input 31 pass (Fig. Zr to the output 28 (until the level changes at the input 32 and the end of the pulse at the input 31).

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Claims (2)

1. CONTROLLED FREQUENCY DIVIDER containing a pulse counter, the inverse outputs of the trigger of each of the digits of which are connected to the first inputs of the corresponding AND-NOT elements, the second inputs of which are connected to the bus of the division ratio code, the outputs are connected to the control the key input, the synchronization input of which is connected to the input bus; the first output — with the counting input of the first trigger of the pulse counter; the reset inputs of the second and subsequent triggers of which are connected between oh, the OR element and the first output bus, characterized in that, in order to extend the functionality by providing the possibility of using the bit outputs of the pulse counter and control of the division factors, the control bus, the second and third output buses are entered into it, and the key has the third output and the switching enable input to the third key output, the switching enable input to the third key output connected to the control bus, the second and third key outputs connected to the first and second output buses, respectively and with the first and second inputs of the OR element, the output of which is connected to the reset inputs of the first and second triggers of the pulse counter, the discharge outputs of which are connected to the third output bus. 2. The divider under item 1, characterized in that the key contains the first and second elements NOT, the first, second, third, fourth and fifth elements OR NOT and the element AND, the first input of the first element OR NOT connected to the first output . key, with the output of the second element OR NOT, with the first input of the element AND with the first input of the third element OR NOT, the output of which is connected to the second output of the key, with the first input of the second element OR NOT and with the first input of the fourth element OR NOT whose second input is connected to the second input of the first element OR NONE, to the second input of the AND element, the third input of which is connected to the switching enable input on the third output of the key connected to the output of the AND element, and to the output of the fifth element OR NONE, the first input which is connected to the output of the first ementa NOR and to a second input of the second OR-NO element, a third input coupled to a second input of the third OR-NO element, with the output of the first NOT element having an input coupled to the input key synchronization, and to a second input 1185600 the fifth element OR NOT, the third input of which is connected to the third input of the second element OR NOT and with the output of the fourth element OR NOT, the third the input of which is connected to the control input of the key and through the second element NOT to the third input of the first element Ta OR NOT.