JP2517943B2 - Timer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention uses an input signal from the outside as a trigger,
The present invention relates to a timer device using a timer circuit that starts automatically.

[Outline of Invention]

According to the present invention, an input signal and a clock signal are supplied, and in a timer device using a timer circuit that generates an output signal after a predetermined time determined by the number of comparison data and clock signals from the timing specified by the input signal, On the other hand, when the first output signal having the first time delay and the second output signal having the second time delay with respect to the input signal are obtained, they are identical to the first and second timer circuits. Comparison data is set, the first and second timer circuits are simultaneously started by the input signal, and after a predetermined time obtained from one timer circuit, different comparisons are made for the first and second timer circuits. Since data is set, the number of interrupt factors is prevented from increasing, and therefore the processing time is shortened.

[Conventional technology]

In the microcomputer, as shown in FIG. 5, an accurate time delay T from the rising edge of the input signal
To generate an output signal with (eg 900 μs) E
A timer device using a timer circuit called TT (External Triggerble Timer) is known.

FIG. 6 shows an example of a conventional timer device. In FIG. 6, a timer circuit (ETT) 21 is surrounded by a broken line. The ETT 21 is supplied with comparison data from the internal bus 22 of the microcomputer, for example. This comparison data is taken in by the data register 23 inside the ETT 21, and transferred from the data register 23 to the comparison register 24. The comparison data from the comparison register 24 is supplied to the match detection circuit 25. The coincidence detection circuit 25 is supplied with the count data of the counter 26, and when both the comparison data and the count data coincide with each other, a detection signal ETE is generated from the coincidence detection circuit 25.

The clock signal via the logic circuit 29 is supplied to the counter 26. The logic circuit 29 is supplied with the input signal from the input terminal 27 and the clock signal from the input terminal 28, and the logic circuit 29 supplies the clock signal to the counter 26 from the rising edge of the input signal, for example. The counting operation starts. The clock signal has a fixed cycle, for example, a cycle of 1 μs. Both the comparison data and the count data are 8-bit data.

The signal ETE from ETT21 is used as a clock input to the D flip-flop 31. The data of the output register 30 is supplied as the data input of the D flip-flop 31. The data from the internal bus 22 is stored in the output register 30, the data is transferred from the output register 30 to the D flip-flop 31 by the signal ETE, and the output signal is obtained at the output terminal 33 via the buffer 32. . The D flip-flop 31 and the buffer 32 form an output port.

Further, the signal ETE from the coincidence detection circuit 25 is taken out to the output terminal 34 and supplied to the comparison register 24 and the counter 26 as a load signal. The comparison register 24 and the counter 26 are loaded with predetermined initial values by the signal ETE. Further, the signal ETE from the ETT21 is supplied to the CPU (not shown). When the signal ETE is generated, the CPU runs the interrupt program. CPU, data register 2
The writing of data to 3 and mode switching are controlled through the internal bus 22.

As shown in Fig. 5, T (900μ
Regarding the operation when obtaining the output signal with the delay of s),
This will be described with reference to FIGS. 7 and 8. The flowchart in Fig. 7 shows the equipment processing before the input occurs and the signal ETE.
2 shows the respective procedures with the interrupt processing performed by the occurrence of. In the preparation process, [FA] (hexadecimal display) corresponding to 250 μs is set in the data register 23 as the comparison data (step). Next, the contents of the data register 23 are transferred to the comparison register 24 (step).

When the input signal is generated, the counter 26 starts counting operation, and the count data of the counter 26 is supplied to the coincidence detection circuit 25. When this count data reaches [FA], the coincidence detection circuit 25 generates a signal ETE. The signal ETE runs the interrupt program. In the interrupt program, it is checked whether the interrupt circuit Ni is 2 (step). (Ni
= 2), 150μ for the data register 23
The comparison data [96] corresponding to s is set (step).

When (Ni ≠ 2] in the step, (Ni = 3)
You can check (step). When the number of interruptions Ni is the third, the low level is set to the output register 30 (step).

The above operation will be described with reference to FIG.
Indicates an input signal, and the counter 26 of the ETT 21 starts counting operation from the rising edge of this input signal. As shown in FIG. 8F, high level data is set in the output register 30. In the data register 23 and the comparison register 24, as shown in FIGS. 8C and 8D, respectively,
In advance, 8-bit data [FA] corresponding to 250 μs has been set. Therefore, the count data of the counter 26 becomes [F
A], the signal ETE shown in FIG. 8B is generated.

By the second signal ETE, the comparison data [96] (150 μs) is set in the data register 23 as shown in FIG. 8C. Therefore, new comparison data [96] is set in the comparison register 24 by the third signal ETE. This third signal ETE sets the output register 30 at a low level as shown in FIG. 8E.

Since the data of the output register 30 is taken in by the D flip-flop 31 by the fourth signal ETE, as shown in FIG. 8E, 150 μ after the third signal ETE is generated.
After s, the output signal falls to low level. Therefore,
From the edge of the input signal (T = 250μs × 3 + 150μs = 90
An output signal with a time delay of 0 μs can be obtained.

The timer device described above obtains one output signal having a time delay T with respect to the input signal, as shown in FIG. As a more complicated case, as shown in FIG. 4, a time delay T1 (for example, 900 μ) with respect to the input signal (FIG. 4A) is used.
s) with a first output signal (FIG. 4B) and a second time delay T2 (eg 910 μs) with respect to the input signal.
The case of obtaining both of the output signals (1) and (2) in FIG. 4C will be described.

FIG. 9 shows an example of a possible configuration for obtaining the first and second output signals having the relationship shown in FIG. Sixth
An output register 35, a D flip-flop 36, and a buffer 37 are added to the configuration shown in the figure, and an output terminal 38 for the second output signal is derived from the buffer 37.

[Problems to be solved by the invention]

In the configuration of FIG. 9 as well, by the same operation as that of the timer device described above, the control of the first output signal having the time delay T1 is delayed by one signal ETE and the control of the second output signal is performed. By controlling, two output signals can be obtained. However, as in the example shown in FIG. 4, when the difference between the time delays T1 and T2 is small, such as (T1 = 900 μs) (T2 = 910 μs), this time difference (10
It is necessary to rewrite the output register 35 between μs). This requires that the processing speed of the CPU is considerably high, and the rewriting process of the output register 35 is impossible when there is only a delay of 10 μs as in the above example.

Therefore, an object of the present invention is to provide a timer device capable of obtaining two or more output signals each having a delay time with a considerably small time difference with respect to an input signal.

[Means for solving problems]

In the present invention, an input signal and a clock signal are supplied, in a timer device using a timer circuit (ETT) that generates an output signal after a predetermined time determined by the number of comparison data and clock signals from the timing specified by the input signal, First timer circuit ETT1 and second timer circuit ETT2
Is provided, the same comparison data is set in the first and second timer circuits ETT1 and ETT2, respectively, and the first and second timer circuits ETT1 and ETT2 are simultaneously started by the input signal, and the first and second timer circuits ETT1 and ETT2 are started. After a predetermined time obtained from one of the timer circuits ETT1 and ETT2, the first and second timer circuits ET
Different comparison data are set for T1 and ETT2, and a first output signal having a first time delay T1 with respect to the input signal is obtained, and a second time delay T2 with respect to the input signal is obtained. A second output signal having is obtained.

[Action]

Two timer circuits ETT1 and ETT2 are provided, and a common input signal and clock signal are supplied to each, and at the same time, the timer operation is started. Further, since the same comparison data is initially set in ETT1 and ETT2, the signals ETE1 and ETE2 are generated at the same timing. If the time delay T1 with respect to the input signal of the first output signal and the time delay T2 with respect to the input signal of the second output signal are (T2> T1), the time determined by the same comparison data initially set is determined a plurality of times. , ETT1 and ETT2 after repeated predetermined time,
Different comparison data are set. This comparison data finally defines the time delays T1 and T2.

According to the present invention, unlike the case where the output buffer is rewritten to obtain the second output signal after the time delay T1, sufficient time for rewriting the output buffer is secured,
Does not need to be very fast. Also, since the interrupt program runs with the signal ETE from one ETT (timer circuit), unlike the interrupt program running with both ETT signals, it is possible to prevent an increase in interrupt factors, and The occupied interrupt processing time can be shortened. Therefore, in the case of a CPU having a slow processing speed, it is possible to avoid the inconvenience that other processing requiring time accuracy cannot be performed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG. 4, a time delay T1 (for example, 900 μs) with respect to the input signal (FIG. 4A) is used.
For the case where both the first output signal (FIG. 4B) having T and the second output signal (FIG. 4C) having the second time delay T2 (eg, 910 μs) with respect to the input signal are obtained. This invention is applied.

As shown in FIG. 1, the first timer circuit (ETE: Extern
al Triggerble Timer) 1 and a second ETT 2 are provided. Comparison data is set in ETT1 and ETT2 via the internal bus 3. Further, the input signal from the input terminal 4 and the clock signal of a constant cycle (1 μs) from the input terminal 5 are supplied to ETT1 and ETT2. ETTT1 and ETT2
Indicates that the comparison data is set in the comparison register from the internal bus 3 via the data register, the clock signal is counted by the counter at the timing synchronized with the rising edge of the input signal, and the count value of the counter and the comparison register are set. The comparison data is compared by the coincidence detection circuit, and when they coincide with each other, signals ETE1 and ETE2 are generated respectively.

The signal ETE1 from ETT1 is used as a clock input to the D flip-flop 10. The data of the output register 8 is supplied as the data input of the D flip-flop 10. The data from the internal bus 3 is stored in the output register 8, the data is transferred from the output register 8 to the D flip-flop 10 by the signal ETE1, and the first output signal is output to the output terminal 14 via the buffer 12. Is obtained. The D flip-flop 10 and the buffer 12 form an output port.

Further, the signal ETE1 from the ETT1 is taken out to the output terminal 6 and supplied to the data register and the counter of the ETT1 as a load signal. A predetermined initial value is loaded into the comparison register and the counter by the signal ETE1. Further, the signal ETE1 from ETT1 is supplied to the CPU (not shown). When the signal ETE1 is generated, the CPU runs the interrupt program. The CPU controls writing of data to the data registers of ETT1 and ETT2 and mode switching through the internal bus 3.

ETT2 has the same configuration as ETT1, and the signal ET from ETT2
E2 is taken out to the output terminal 7 and used as a clock input to the D flip-flop 11. D flip-flop 11
Is supplied with data from the output register 9, and the output signal of the D flip-flop 11 is taken out to the output terminal 15 via the buffer 13 as the second output signal. CPU is ETT
Enables interrupts only from signal ETE1 from 1
2 does not enable interrupts.

As shown in FIG. 4, for the input signal (FIG. 4A)
Operation for obtaining the first output signal (FIG. 4B) having a delay of T1 (900 μs) and the second output signal (FIG. 4C) having a delay of T2 (910 μs) with respect to the input signal Will be described with reference to FIGS. 2 and 3.

The flowchart of FIG. 2 shows the respective steps of the preparatory processing before the input is generated and the interrupt processing performed by the generation of the signal ETE1. In the preparation process, the data register of ETT1 corresponds to 250 μs as comparison data [FA]
(Hexadecimal display) is set (step). Similarly,
Corresponds to the data register of ETT2 with 250 μs [FA] (16
Display) is set (step). Next, the contents of the data register are transferred to the comparison register of ETT1 (step). Similarly, the contents of the data register are transferred to the comparison register of ETT2 (step).

When an input signal is generated, the counters of ETT1 and ETT2 start counting operation, and when the count data of the counter reaches [FA], signals ETE1 and ETE2 are generated. Only the signal ETE1 runs the interrupt program. In the interrupt program, it is checked whether the interrupt count Ni is 2 (step). In the case of (Ni = 2), the comparison data [96] corresponding to 150 μs is set in the data register of ETE1 (step). Next, in the data register of ETT2
Data [A0] corresponding to 160 μs is set (step).

When (Ni ≠ 2) in the step, (Ni = 3)
You can check (step). When the number of interruptions Ni is the third, the low level is set to the output register 8 (step). Next, the output register 9
A low level is set for (step).

The above operation will be described with reference to the time chart of FIG. 3. FIG. 3A shows an input signal, and the counters of ETT1 and ETT2 start counting operation from the rising edge of this input signal. High-level data is set in the output register 8 as shown in FIG.
Is set to high level data as shown in FIG. 3J. As shown in FIGS. 3D, 3E, 3F and 3G, the ETT1 and ETT2 data registers and comparison registers have 8-bit data [FA] corresponding to 250 μs in advance. Is set. Therefore, ETT1 and
From ETT2, signals ETE1 and ET shown in FIG. 3B and FIG. 3C are generated each time the count data of each counter becomes [FA].
E2 occurs.

The second time signal ETE1 causes the data register of ETT1 to compare data [96] (150 μm) as shown in FIG. 3D.
s) is set. Therefore, the new comparison data [96] is stored in the comparison register of ETT1 by the third signal ETE1.
Is set. By this third signal ETE1, the output register 8 is set to a low level as shown in FIG. 3H.

On the other hand, the second time signal ETE1 causes the comparison register [A0] (16
0 μs) is set. Therefore, the third comparison signal ETE1 causes a new comparison data [A
0] is set. By this third signal ETE1,
A low level is set in the output register 9 as shown in FIG. 3J.

The data of the output register 8 is changed by the fourth signal ETE1.
Since it is taken into the D flip-flop 10, as shown in FIG. 3I, 150 μs after the third signal ETE1 is generated.
After that, the first output signal falls to the low level. Therefore, from the edge of the input signal (T = 250μs × 3 + 150μs
A first output signal with a time delay of = 900 μs) is obtained.

Similarly, the data in the output register 9 is the fourth signal ETE1.
Is taken into the D flip-flop 11 by, so as shown in FIG. 3K, after the third signal ETE1 is generated.
After 160 μs, the third output signal falls to low level. Therefore, from the edge of the input signal (T = 250 μs × 3
A second output signal with a time delay of +160 μs = 910 μs) is obtained.

The present invention can be applied to the case where three or more output signals having mutually different time delays are obtained with respect to the input signal, similarly to this embodiment.

〔The invention's effect〕

In the present invention, a plurality of timer circuits operate in synchronization with a common input signal and clock signal, and the interrupt program runs using only the signal ETE1 from one timer circuit. Therefore, according to the present invention, a plurality of output signals having slightly different delay times can be obtained by the CPU having a slow processing speed. Further, according to the present invention, since the interrupt factors do not increase, it is possible to prevent the processing time from increasing.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the embodiment, FIG. 3 is a time chart showing the operation of the embodiment, and FIG. 4 is an input of the embodiment. FIG. 5 is a waveform diagram showing the relationship between signals and output signals, FIG. 5 is a waveform diagram used to explain a timer circuit usable in the present invention, and FIG.
FIG. 7 is a block diagram of a timer circuit that can be used in the present invention, FIGS. 7 and 8 are flow charts and time charts used for explaining the timer circuit that can be used in the present invention, and FIG. 9 is used as a reference for explaining the present invention. It is a block diagram of another example of a timer device. Description of main symbols in the drawings 1,2: ETT, 3: Internal bus, 4: Input signal input terminal, 5: Clock signal input terminal, 8,9: Output register, 10,11: D flip-flop, 14 , 15: Output terminal.

Claims (1)

(57) [Claims] 1. A timer device using a timer circuit, which is supplied with an input signal and a clock signal, and generates an output signal after a predetermined time determined by the number of the comparison data and the number of the clock signals from the timing defined by the input signal. A first timer circuit and a second timer circuit are provided, the same comparison data is set in the first and second timer circuits respectively, and the first and second timer circuits are simultaneously started by an input signal, After a predetermined time obtained from one of the first and second timer circuits, the first and second timer circuits
Different comparison data are set to the timer circuit of 1) to obtain a first output signal having a first time delay with respect to the input signal and a second time with respect to the input signal. A timer device characterized in that a second output signal having a delay is obtained.