JPH04308909A - Pulse generator - Google Patents

Abstract

PURPOSE:To easily generate a pulse signal with an arbitrary pulse width or waveform. CONSTITUTION:The pulse generator is equipped with a timer 1 capable of an up/down count, which switches the count direction of a clock signal CLK in a constant cycle by a count direction switching signal (c) from an outside, a first register 2 which stores a count direction switching value A, a first comparator 3 which compares the count direction switching value A with the timer count value CNT of the timer 1, and outputs a first coincidence detecting signal (a) when both of them are coincident, and a count direction controller 4 which applies the count direction switching signal (c) to the timer 1 when the first coincidence detecting signal (a) is inputted. And also, the pulse generator is equipped with a second register 5 which stores a pulse width setting value B which normalizes the width T of an output pulse signal POUT, a second comparator 6 which compares the pulse width setting value B with the timer count value CNT of the timer 1, and outputs a second coincidence detecting signal (d) when both of them are coincident, and an output controller 7 which inverts and outputs the signal polarity of the output pulse signal POUT at each time when the second coincidence detecting signal (d) is inputted.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a pulse generator,
The present invention relates to a pulse generator suitable for use in a microcontroller that requires time control, for example.

A microcontroller has a timer built-in or as a peripheral circuit for performing various timing controls. Timing pulses used for timing control are required to have various time widths depending on the application, and the setting and adjustment of the time width is required to be simple.

0003

2. Description of the Related Art Examples of conventional timers are schematically shown in FIGS. 4 and 5.

[0004] This timer includes a free run timer 100,
It is composed of a comparator 102, a comparison value register 101, and a terminal output/interrupt control section 103. The free-run timer 100 continues to count at a constant cycle after startup, and when a match occurs between the comparison value register 101 and the timer value, the output/interrupt control unit 103 outputs the terminal output POUT or interrupt signal IN.
It is configured to generate T, and by rewriting the set value X of the comparison value register 101 every time a comparison match occurs,
Generates arbitrary intervals and outputs waveforms.

[0005] Also, a comparator 102 and a comparison value register 10
1 has multiple channels, it is possible to control complex waveforms, etc.

FIG. 5 shows an example of waveform output using a timer of the type shown in FIG. In this figure, the horizontal axis is time and the vertical axis is the timer count value CNT. When the timer starts, the comparison value X of the comparison value register 101 is set to the value of ■, and the timer count value CNT and comparison value X match. Time (t1)
Inverts the terminal output POUT and stores it in the comparison value register 101.
Set the time ■ to invert the next waveform. In this way, it is necessary to calculate and set the data of the comparison value X in accordance with the changing timing of the waveform.

Other examples of conventional timers are shown in FIGS. 6 and 7.
Shown below.

This timer is composed of a reloadable (resettable) down count timer 105, a reload value setting register 104, and a terminal output/interrupt control section 103. By starting the timer, reload value setting register 1
The value Y of the reload value setting register 104 is reset to the down count timer 105 and the counting operation is continued when the down count timer 105 underflows. . The configuration is such that waveform output control and interrupt generation are performed every time the down count timer 105 underflows, and arbitrary interval generation and waveform output are performed by rewriting the value Y of the reload value setting register 104 every time the reload operation is completed. ing.

FIG. 7 shows an example of waveform output using the timer of the format shown in FIG. In this diagram, at startup,
The down count timer 105 is set to a value of ■, and the reload value setting register 104 is set to a value of ■. Due to the underflow of the down-count timer 105, the value of ■ is set in the down-count timer 105, and the counting operation continues until the next underflow.
It is necessary to set the value in the reload value setting register Y.

0010

[Problem to be Solved by the Invention] The timer shown in FIG.
By providing a plurality of comparison value registers for one timer channel, it is possible to control independent terminals, which has the advantage of reducing the amount of hardware.

However, since this timer sets the comparison value X for the free-run timer 100, calculations are required during the setting, which has the drawback of reducing the processing power of the CPU.

On the other hand, the timer shown in FIG. 6 has the advantage that the pulse width of the output waveform can be set as an absolute value by setting the reload value Y, so there is no need for calculation, and the load on the CPU is lightened.

However, this timer has the disadvantage that in order to independently control multiple channels, timers and reload registers for the number of channels are required, and when attempting to control multiple channels, the amount of hardware becomes large.

An object of the present invention is to provide a pulse generator that can easily generate pulse signals of arbitrary pulse widths or waveforms.

[0015]

[Means for Solving the Problems] The present invention provides a method for counting a clock signal (CLK) having a constant period by switching the counting direction to either up or down using a counting direction switching signal (c) from the outside. a timer (1) capable of counting down; a first register (2) storing a count direction switching value (A) for switching the counting direction of the timer (1); Timer count value (CNT) of timer (1)
), and when both values match, the first match detection signal (
a); and a count direction controller (4) that provides a count direction switching signal (c) to the timer (1) when the first coincidence detection signal (a) is input. and the width (T) of the output pulse signal (POUT)
), the pulse width setting value (B) and the timer count value (CNT) of the timer (1) are compared, and both values are determined. a second coincidence detection signal (d) that outputs a second coincidence detection signal (d) when the two match;
The device includes a comparator (6) and an output controller (7) that controls the output pulse signal (POUT) every time the second coincidence detection signal (d) is input.

[0016]

According to the present invention, the count direction switching value (A) is set in the first register (2), and the pulse width setting value (B) is set in the second register (5). A clock signal (CLK) is applied to the timer (1), and the timer (1) performs a counting operation on this clock signal (CLK). The counting direction of the timer (1) is assumed to be, for example, up when the timer count value (CNT) is 0, and to be down when the timer count value (CNT) is equal to the count direction switching value (A). Now, the timer (
1) performs a count-up operation, the timer count value (CNT) at that time is given to the first comparator (3) and the second comparator (6) from time to time. On the other hand, the first comparator (3) is given the count direction switching value (A) from the first register (2), and the second comparator (6) is given the pulse width setting value (A) from the second register (5). B) is given. As the timer (1) counts up, the first comparator (3) outputs the count direction switching value (A) and the timer count value (CNT
), and the second comparator (6) compares the pulse width setting value (B) with the timer count value (CNT). If the value of the pulse width setting value (B) is relatively lower than the value of the count direction switching value (A), the second comparator (
6) is timer count value (CNT) = pulse width setting value (
At the time of B), that is, when both values match, the second match detection signal (d) is output to the output controller (7). The output controller (7) receives the second coincidence detection signal (d) and inverts the signal polarity of the output pulse signal (POUT). That is, for example, the previous output pulse signal (POUT) = L
If so, raise it to H. At this time, the timer (1) continues to count up, and the timer count value (C
When NT)=A, the first comparator (3) outputs the first coincidence detection signal (a) to the count direction controller (4). The counting direction controller (4) receives the first coincidence detection signal (a) and outputs a counting direction switching signal (c) to the timer (1). This counting direction switching signal (c) causes the timer (1) to change the counting direction from counting up to counting down. When the timer count value (CNT) equals the pulse width setting value (B) due to countdown, the second comparator (6) outputs the second coincidence detection signal (d) to the output controller (7). . The output controller (7) receives the second coincidence detection signal (d) and inverts the signal polarity of the output pulse signal (POUT), changing the output pulse signal (POUT) from H to the output pulse signal (POUT). POUT)=lower to L. In this way, the output pulse signal (POUT) rises due to the second coincidence detection signal (d) when the timer (1) counts up.
The output pulse signal (POUT) falls due to the second coincidence detection signal (d) during the next countdown, and the pulse width (T) of the output pulse signal (POUT) is determined.

[0017]

Embodiments Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 shows an embodiment of a pulse generator according to the present invention. As shown in Figure 1, the pulse generator is timer 1
have. Timer 1 is configured using an up/down counter, and counts up and counts down a clock signal CLK of a constant period inputted from the outside. This switching of the counting direction is performed in synchronization with the input timing of the counting direction switching signal c.

[0019] Also, timer 1 has a timer count value CNT.
=0, a zero detection signal b is output to the count direction controller 4. The timer 1 constantly outputs a timer count value CNT that changes from moment to moment to the first comparator 3 and the second comparator 6.

On the other hand, the pulse generator has a first register 2 . The first register 2 stores an arbitrary count direction switching value A given from the outside, and outputs the count direction switching value A to the first comparator 3 in the form of parallel data.

Similarly, the pulse generator has a second register 5. The second register 5 stores an arbitrary pulse width setting value B given from the outside, and outputs the pulse width setting value B to the second comparator 6 in the form of parallel data.

The first comparator 3 compares the count direction switching value A and the timer count value CNT, and when the two values match (CNT=A), outputs a first coincidence detection signal a to the count direction controller 4. do.

The count direction controller 4 is a timing controller that outputs a count direction switching signal c triggered by the first coincidence detection signal a or zero detection signal b, and when the first coincidence detection signal a or zero detection signal b is inputted. When this occurs, a count direction switching signal c is output to timer 1.

The second comparator 6 compares the pulse width setting value B and the timer count value CNT, and when the two values match (C
NT=B), the second coincidence detection signal d is output to the output controller 7.

The output controller 7 outputs an output pulse signal PO whose polarity is inverted at the timing when the second coincidence detection signal d is input.
This is a pulse generation circuit consisting of a Schmitt trigger circuit, etc. that generates UT. This output controller 7, if necessary,
Outputs interrupt signal IR.

Next, the operation of FIG. 1 will be explained with reference to FIG. First, as a premise, the first
It is assumed that the count direction switching value A set in the register 2 is a value relatively larger than the pulse width setting value B set in the second register 5.

Now, assume that the pulse generator is activated by a timing controller (not shown). Then, the timer 1 starts counting up the clock signal CLK starting from the timer count value CNT=0. Along with this,
The timer count value CNT increases sequentially, and the timer count value CNT is provided to the first comparator 3 and the second comparator 6, respectively. The first comparator 3 compares the timer count value CNT that is inputted every moment with the count direction switching value A. Similarly, the second comparator 6 also compares the timer count value CNT and the count direction switching value A.
NT and pulse width setting value B are compared. Assuming that the timer count value CNT increases and becomes equal to the pulse width setting value B (time tB1), the second comparator 6 outputs the second coincidence detection signal d to the output controller 7. At this time, the output controller 7 causes the output pulse signal POUT to rise at time tB1 and inverts the polarity (from L to H in logic level). Furthermore, the timer count value CNT
Suppose that the timer count value CNT becomes equal to the count direction switching value A (time tAH1), then the first
A first coincidence detection signal a is outputted from the comparator 3 to the count direction controller 4. At this time, the count direction controller 4 outputs the count direction switching signal c to the timer 1 at time tAH1. The timer 1 receives the counting direction switching signal c and switches the counting direction from counting up to counting down. As a result, the timer count value CNT of timer 1 decreases sequentially. As the timer count value CNT decreases, when the timer count value CNT=pulse width setting value B (time tB2), the second comparator 6 outputs the second coincidence detection signal d again. This second coincidence detection signal d causes the output controller 7 to output the output pulse signal POUT.
Inverts the polarity of the signal (from H to L at logic level). In this way, the output pulse signal PO rising at time tB1
UT falls at time tB2, and an output pulse signal POUT having a pulse width T is generated. Furthermore, the timer count value CNT decreases, and the timer count value CNT
=0, the timer 1 outputs the zero detection signal b to the count direction controller 4 (time tAL1). At this time,
The count direction controller 4 outputs a count direction switching signal c to the timer 1. Timer 1 receives the count direction switching signal c and switches the counting direction from countdown to countup. As a result, timer 1 starts counting up again, and the same operation as above is repeated.
An output pulse signal POUT having a pulse width T determined by the count direction switching value A and the pulse width setting value B is outputted from the output controller 7. Therefore, the output pulse signal P
If it is desired to change the pulse width T of OUT, the pulse width setting value B may be changed first, or the count direction switching value A may be changed. Whether to change the pulse width setting value B or the count direction switching value A depends on the magnitude of the pulse width T, and changing the count direction switching value A is effective for major setting changes.

Next, another example of the pulse generator according to the present invention is shown in FIG. This embodiment embodies the functions shown in FIG. 1 at the IC chip level.

In FIG. 3, the pulse generator includes a timer unit control section 8 that controls the overall timing of the pulse generator and has the functions of the count direction controller 4 of FIG. 1;
A compare buffer register 9 that temporarily stores the count direction switching value A and the pulse width setting value B, and the first
register 2, first comparator 3, second register 5 and second
a compare register 10 that includes the function of a comparator 6; a prescaler 12 that divides the internal clock signal CLK1;
External clock signal CLK2 or prescaler 12
a selector 13 that selects and outputs one of the outputs according to a control signal from the timer unit control section 8;
The output controller 11 corresponds to the output controller 7 in FIG. 1. The timer unit control section 8, compare buffer register 9, and 16-bit timer 14 are connected to a host device (not shown) via a data bus 15, and are supplied with necessary data.

In the above configuration, the 16-bit timer 1
4 has an up/down function, and when the timer count value CNT of the 16-bit timer 14 and the value of the compare register 10 (count direction switching value A) match, the timer unit control section 8 changes the count direction of the 16-bit timer 14. is switched to down counting, and switched to up counting upon detection of timer count value CNT=0. Then, 16-bit timer 14 and compare register 1
0 and outputs an output pulse signal POUT via the output controller 11.

[0031]

As described above, according to the present invention, a count direction switching value and a pulse width setting value are set, and an output pulse signal of an arbitrary pulse width is generated by comparing these values with a timer count value. Therefore, it can be widely used as a pulse generator for various timing controls.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of FIG. 1;

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional timer.

FIG. 5 is a waveform diagram showing the operation of FIG. 4;

FIG. 6 is a block diagram showing another example of a conventional timer.

FIG. 7 is a waveform diagram showing the operation of FIG. 6;

[Explanation of symbols]

1...Timer 2...First register 3...First comparator 4...Count direction controller 5...Second register 6...Second comparator 7...Output controller 8...Timer unit control section 9...Compare buffer register 10...Compare register 11...Output controller 12...Prescaler 13...Selector 14...16bit timer 15...Data bus 100...Free run timer 101...Comparison value register 102...Comparator 103...Output controller 104...Reload value setting register 105...Down count timer A...Count direction switching value B...Pulse width setting value CLK...clock signal CLK1...Internal clock signal CLK2...external clock signal CNT…Timer count value IR...Interrupt signal POUT...Output pulse signal T...Pulse width X…Comparison value Y...Comparison value a...First coincidence detection signal b...Zero detection signal c...Count direction switching signal d...Second coincidence detection signal

Claims (1)

[Claims] 1. A timer (1) capable of up/down counting that switches a clock signal (CLK) of a constant period to either up or down in response to an external count direction switching signal (c).
), and a first register (A) for storing a count direction switching value (A) for switching the count direction of the timer (1).
2), the count direction switching value (A), and the timer (
a first comparator (3) that compares the timer count value (CNT) of 1) and outputs a first coincidence detection signal (a) when the two values match; When input, the timer (1) receives a count direction switching signal (c
); a second register (5) that stores a pulse width setting value (B) that defines the width (T) of the output pulse signal (POUT); ) and the timer count value (CNT) of the timer (1), and outputs a second coincidence detection signal (d) when both values match; An output controller (7) that controls the output pulse signal (POUT) every time the signal (d) is input.
A pulse generator comprising: