SU1358063A1 - Digital phase-frequency comparator - Google Patents

Abstract

The invention can be used for the correction and synchronization of frequencies in systems of control and automatic control of frequency. The purpose of the invention is to increase the accuracy of the device. The comparator contains counters I and 2 pulses, triggers 5 and 7, the element NOT 6, the element OR 8. The introduction of the elements AND-HE 9 and 10, the elements 11,13 and 14, the trigger 12 and the output bus 16 and 17 eliminates the uncertainties of the output signal when the input signal coincides in frequency and phase. 4 il. 3 / od1 wb / JfOffl 15 cl fZ. Output 3 with SP CX) O5 with Srig.1

Description

The invention relates to a pulse technique and can be used in radio and electrical devices for various purposes, as an example for frequency correction and synchronization in control systems and automatic control often.

The purpose of the invention is to increase the accuracy by eliminating the uncertainty of the output signal when the input signals coincide in frequency and phase.

Fig. 1 shows a structural electrical circuit of the device; on - 4 - timing diagrams for how the device works.

The device contains the first and second counters 1 and 2 pulses, the clock inputs of which are connected respectively to the first and second input buses 3 and 4, and the R inputs of counters 1. and 2 are connected to the inverse output of the first trigger 5, whose 1 input is NOT 6 is connected to the bus 3. The output of the counter 1 is connected to the 1-input of the second trigger 7, the first input of the element OR 8 and the first input of the first AND-NOT 9, the output of which is connected to the first input of the second element AND-NOT 10, the output of which soy, dinen with the first input of the first element And 11 and 1 input trigger 1 2. The direct and inverse outputs of the second trigger 7 are connected to the first inputs of the second and third elements 13 and 14, respectively, the outputs of which are connected respectively to the first and second output buses 15 and. 16, the inverse output of the third trigger 12 is connected to the third output bus 17, and the direct output is connected to the second inputs of the AND elements 13 and 14. The output of the counter 2 is connected to the K-input of the trigger 7, the second inputs of the OR element and the first element NOT 9, the output of which is connected to the K-input of the trigger 12 and the second input of the AND 11 element, the output of which is connected to the K-input of the trigger 5. In addition, the output of the OR element 8 is connected to the second input of the AND-HE element 10,

The time diagrams of the device operation are shown for the following cases (the capacity of counters 1 and 2 is assumed to be 4): the frequency of the signal on bus 3 is greater than the frequency of the signal on bus 4 (Fig 2), the signal on bus 3 coincides

in frequency and phase with a signal on bus 4 (FIG. 3), the frequency of the signal on bus 3 is lower than the frequency of the signal on bus 4 (FIG. 4).

The following time diagrams are shown (Fig.2-4) s on the input bus 3 (a), on the input bus 4 (b), at the output of the element HE 6 (c), at the inverse output of the trigger 5 (g), at the output counter 1 (d), at the output of counter 2 (e), at the output of the element OR 8 (g), at the output: -: element AND-NOT 9 (h), at the output of the element AND-NOT 10 (and), at the output And 11 (k), at the direct output of the trigger 5 (l), at the direct trigger trigger 12 (m), at the inverse output of the trigger 12- (n), at the output of the element I 13 (o), at the output of the element And 14 (p).

The device works as follows

 Controlled pulse sequence with frequency fj arrives

on the bus 4 devices. On the bus 3 of the device receives a reference sequence of pulses with a frequency f,. This sequence is a reference in frequency and phase. The moment of signal change from the logical level. Whose zero to one corresponds to the beginning of each period.

In the initial state, on the frung output of the trigger 5 is set

the level of the logical unit, which, by the reset inputs, keeps the counters 1 and 2 in the initial state of the logical zero. The change of the signal at the inverse output of the trigger 5 from the level of the logical unit to the zero level coincides with the beginning of the reference signal period. In connection with this, the beginning of the counting of pulses by both counters, i.e. the beginning of the control, coincides with the beginning of the period of the reference signals.

If the frequencies f, are equal to f and

in phase (Fig. 3), the signals at the outputs of counters 1 and 2 appear at the same time. This leads to a change in the signal level at the output of the first element AND-HE 9 from the level of the logical unit to the level of logic zero and the installation of the third trigger 12 to the state of logic zero on its

direct exit. Simultaneously with the change of the state of the element AND-NOT 9, the first input of the element AND-NE 10 receives a signal of logical zero, which prohibits the passage of pulses

from the element OR 8, blocking by this the switching of the trigger 12 to the 1-input of the Trigger 7, with equal frequencies in magnitude and phase, changes its state after each comparison cycle. However, the logical zero signal from the direct output of the trigger 12 keeps the logic zero level at the outputs of the elements 13 and 14. Thus, when frequencies are equal in magnitude and phase, the output of the device establishes the unambiguous status of the device: the level of logical zero on buses 15 and 16 and the level of logical unit on bus 17. After the end of the comparison cycle, the signal level at the output of the element 1 G changes the level of logic zero and switching of the trigger 5 to the initial state takes place.

If the frequencies are equal in magnitude, but differ in phase, or one of the input frequencies is greater than the other, then at the end of the comparison cycle, at the output of AND-HEN 9, there is a logical one level that permits the signal from the output of the OR-8 element to the trigger input 12. At the same time, trip 12, when a pulse is detected at the output of any of the counters 1 or 2, switches to the state of a logical unit at its direct output. Moreover, if the signal phase on bus 3 is the leading one or the signal frequency on bus 3 is higher than the frequency of the signal on bus 4 (FIG. 2), counter 1 reads first and switches trigger 7 to the state of logical unit at its direct output. In this case, the logical unit level is also set on the code of the AND 13 element. Thus, if the phase of the reference sequence is leading, a unique status is also established on the device bus: the level of logical unit on bus 15 and the level of logical zero on buses 1 6 and 1 7.

Similarly, when the leading phase of the signal on bus 4 or the frequency of the signal on bus 4 is higher than the frequency of the signal on bus 3, the output of the AND 14 element sets the level of the logical unit, the output of the AND 13 element and the inverse output of the trigger 12 is the logic zero level (FIG. .four).

Thus, in the proposed device, compared with the known one, the uncertainty of the output information is eliminated for the case when the frequencies coincide in magnitude and phase. This improves the accuracy of the device and allows its use in automatic control systems.

Claims (1)

Invention Formula 0 five five 0 Digital phase frequencies A new comparator containing the first and second pulse counters, the clock inputs of which are connected respectively to the first and second input buses, and the R inputs to the inverse output of the first trigger, the 1 input of which is NOT connected to the first input bus, the output The first pulse counter is connected to the 1 input of the second wave and to the first input of the OR element, and the output of the second pulse counter is connected to the K input of the second trigger and the second input of the OR element, as well as the first output bus, which is with what To improve accuracy by eliminating the output uncertainty when the input signals coincide in frequency and phase, the second and third output buses, the first and second AND-NOT elements, the third trigger and the first, the second and third AND elements are entered into it, the first inputs the second and third elements And are connected respectively with the direct and inverse outputs of the second trigger, the outputs of the second and third elements And are connected respectively with the first and second output buses, and the second input with the direct output of the third trigger, The pc output of which is connected to the third output bus, the 1-input is connected to the output of the second AND-N element and the first input of the first element is AND, the K-input is connected to the output of the first AND-NAND element, the first input of the second AND-NAND element and the second input The first element AND, the output of which is connected to the K input of the first trigger, the output of the OR element connected to the second input of the second NAND element, and the first and second inputs of the first AND NAND element are connected respectively to the outputs of the first and second pulse counters. five 0 0 ti, tf  LпJlJlJnJlJтлJтпJlJlJlJlJl.  l-rbrunjlJlJlJlJlJ4JlJlJTjnj L