JPH05282069A - Timer device - Google Patents

Abstract

PURPOSE:To perform pulse output control over a timer by the timer device at more precise timing in synchronism with interruption. CONSTITUTION:A control register which controls the start and stop of the counting operation of the counter 100-1 of the timer device counting a count clock is of master-slave constitution and control information set in a master-side control register 100-2-2 is transferred to a slave-side control register 200-2-2 to start the counting operation of the counter 100-1. Consequently, the counting operation of the counter of the timer device can be started through hardware in synchronism with an interruption signal, so the pulse output control over the timer can be performed at the precise timing from the generation of the interruption signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer device having a pulse output function, and more particularly to a timer device which controls a pulse output operation of a timer by an external interrupt.

[0002]

2. Description of the Related Art An example of the function and operation of a conventional timer will be described with reference to the drawings.

FIG. 3 shows an example of a conventional timer. CP
The U1000 is an arithmetic unit that outputs control data for starting and stopping the pulse output operation of the timer to the timer 100.

The conventional timer 300 includes a counter 100-1 for counting the count clock 2000, a control register 300-1 for controlling start and stop of counting operation of the counter, and a count value of the counter 100-1. The comparison register 100-3 and the comparison register 100-4, which are registers for setting the coincidence timing, are compared with the comparison register 100-3 and the counter 100-1, and if they coincide, a coincidence signal 100-7 is output. Comparator 100-
5, the comparison register 100-3 and the counter 100-1 are compared, and if they match, a comparator 100-5 that outputs a match signal 100-8 and a match signal 100-7 of the comparator are set to 1. It is composed of an SR flip-flop 100-9 which is reset by the coincidence signal R of the comparator 100-6.

Next, the operation of the conventional example will be described. In the conventional example, a single output operation using a timer will be described.

Before starting the timer, the comparison register 100-3 stores the time m until the output waveform shown in FIG. 4 changes from 0 to 1, and the comparison register 10-3 stores the time m.
For 0-4, the time n until the output waveform changes from 1 to 0 is stored.

To start the timer 300, the CPU 1000 sets the value of the control register 300-1 to 1, so that the counter 100-1 starts counting up the input internal clock.

When the value of the control register 300-1 is set to 0, the value of the counter 100-1 is cleared and counting up is stopped.

When the count value of the counter 100-1 coincides with the value of the comparison register 100-3, the comparator 100-5 outputs a coincidence signal 100-7, which is sent to the set side of the SR flip-flop 100-9. When 1 is input, the output waveform changes from 0 to 1.

Next, the count value of the counter is compared with the comparison register 10.
When it matches the value of 0-4, the comparator 100-8 outputs the match signal 100-8, and the SR flip-flop 100
1 is input to the reset side of -9, and the output waveform is from 1 to 0.
Change to. As a result, a single pulse determined by m and n is output, as shown in FIG.

The timer 1 is synchronized with the interrupt signal 3000.
When controlling the pulse output of 00, the CPU 100
By writing 1 to the control register 300-1 in the interrupt routine that accepts the interrupt generated by 0 and starts the pulse output of the timer,
Counter starts counting operation.

FIG. 5 shows the timing from the generation of an interrupt to the start of pulse output.

T1 is the time from the occurrence of an interrupt until the CPU accepts the interrupt. T2 is the time from when the CPU accepts the interrupt until the counting operation of the timer is started in the interrupt routine.

[0014]

In the conventional timer, when the timing control of the pulse output is performed in synchronization with the interrupt, the CPU accepts the generated interrupt and then executes the interrupt routine, in which the timer counts. Start operation. At the time of an interrupt, the conventional timer does not work because the interrupt acceptance timing of the CPU differs depending on the status of other interrupt requests and the instruction execution status of the CPU, and it takes time from interrupt acceptance to register setting in the interrupt routine. It is not possible to start the counting operation of the timer exactly in synchronization with an interrupt,
Accurate timing control was difficult from interrupt generation to timer output.

It is an object of the present invention to provide a timer device which controls a pulse output of a timer at a more accurate timing in synchronization with an interrupt.

[0016]

In order to achieve the above object, a timer device according to the present invention comprises a counter for counting a count clock and two comparison registers for setting coincidence timing of the count value of the counter. And two comparators that compare the count value of the counter with the set values set in the two comparison registers and output a match signal when they match, and a pulse controlled by the match signal. And a control means for controlling the start and stop of the counting operation of the counter, wherein the control means has a master / slave configuration of a master side storage means and a slave side storage means. By transferring from the master side storage means to the slave side storage means in synchronization with the interrupt signal from Start the count operation is for timer output from the timer output unit.

Further, it has a selection register for selecting a control method for starting and stopping the counting operation of the counter.

[0018]

The timer pulse output control is performed at a highly accurate timing by starting the counting operation of the counter of the timer device by hardware in synchronization with the interrupt signal.

[0019]

The present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention.

In FIG. 1, a CPU 1000 is an arithmetic unit that outputs control data for starting and stopping a pulse output operation of the timer to the timer 100 of the present invention.

The timer 100 has a count clock 20.
A counter 100-1 for counting 00, a control register for controlling start and stop of counting operation of the counter,
If the comparison register 100-3 and the comparison register 100-4, which are registers for setting the coincidence timing with the count value of the counter 100-1, and the comparison register 100-3 and the counter 100-1 are compared and coincident, The comparator 100-5 which outputs the coincidence signal 100-7, and the comparator 100-6 which compares the comparison register 100-4 and the counter 100-1 and outputs the coincidence signal 100-8 if they coincide with each other.
And an SR flip-flop 100-9 which is set 1 by the coincidence signal 100-7 of the comparator 100-5 and reset by the coincidence signal 100-8 of the comparator 100-6.

The control register is the control register 100-2.
-1 and the control register 100-2-2 have a master / slave configuration, and the control register 100 on the master side is
In 2-1, data is written from the CPU, and the value of the control register 100-2-2 on the slave side is used for timer 1
The counting start and stop of the counter 100-1 of 00 is controlled.

The value of the control register 100-2-2 is "1".
At the time of, the counter 100-1 is counted up, and at the time of "0", the counting is stopped. Further, in synchronization with the interrupt signal 3000, the control register 100 on the master side
2-1 is the slave side control register 100-
2-2 is transferred.

Next, the operation of this embodiment will be described.
In this embodiment, a case where the pulse output control of the timer 100 is started by the interrupt signal 3000 will be described.

First, as an initial setting of the timer 100, an arbitrary value is set in the comparison register 100-3 and the comparison register 100-4. In this embodiment, as an example, "0FH" is set in the comparison register 100-3 and "1FH" is set in the comparison register 100-4.

In order to start the counting operation of the counter 100-1 of the timer 100, the CPU sets the operation permission information "1" of the timer 100 in the control register 100-2-1.
To set. However, at this stage, the control register 100
The value "1" set in the control register 100-1 has not yet been transferred to the 2-2-2, and the slave side control register 1
Since the value of 00-2-2 is “0”, the counter 100
The count clock 2000 is not supplied to -6, and the timer 100 stops operating.

In this state, the interrupt signal 3000
Becomes active “1”, the control register 1
The contents of 00-2-1 are transferred to the control register 100-2-2 in synchronization with the interrupt signal 3000. By transferring “1” to the control register 100-2-2, the count clock 2000 is sent to the counter 100-1.
Is supplied, and the timer 100 starts the counting operation in synchronization with the interrupt signal 3000.

The count value of the counter 100-1 is "0FH".
Therefore, when the value "0FH" in the comparison register 100-3 matches, the comparator 100-5 determines that the match signal 100
Output -7. This coincidence signal 100-7 becomes an input signal on the set side of the SR flip-flop 100-9 that outputs a pulse, and the output pulse of the timer 100 is 0.
Changes from 1 to 1. Next, the count value of the counter 100-1 becomes “1FH”, and the value of the comparison register 100-4 becomes “1FH”.
If it matches H ", the comparator 100-6 outputs a match signal 100-8. The match signal 100-8 is
S / R flip-flop 100-9 for pulse output
, Becomes the input signal on the reset side, and the output pulse changes from 1 to 0.

FIG. 6 is a diagram showing the timing from the generation of an interrupt to the start of pulse output.

From the occurrence of the interrupt, T1 is the timer 100.
This is the time until the counting operation of the counter 100-1 is started.

(Second Embodiment) FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In FIG. 2, the CPU 1000 is an arithmetic unit for outputting control data for starting and stopping the pulse output operation of the timer to the timer 200 of the present invention.

The timer 200 includes a counter 100-1, a control register 100-2-1 and a control register 100-2-.
2, comparison register 100-3, comparison register 100-
4, comparator 100-5, comparator 100-6, coincidence signal 1
The operation of 00-7, the coincidence signal 100-8, and the SR flip-flop 100-9 is the same as the operation described in the first embodiment.

The selection register 200-1 includes a counter 10
It is a register that selects a control method for starting and stopping the counting operation of 0-1. The selection register 200-1 has a CPU
The selection signal “1” or “0” is set by 1000.

The CPU 1000 is added to the selection register 200-1.
Therefore, if the selection signal “1” is set,
The control for starting and stopping the counter 100-1 is performed in synchronization with the interrupt signal 3000 described in (1).

On the other hand, when the selection signal "0" is set, the CPU 1000 sets the timer 20 at an arbitrary timing.
It controls the start and stop of the counting operation of the counter 100-1 of 0.

Hereinafter, the operation from the start to the stop of the pulse output operation of the timer is the same as that shown in the first embodiment.

As described above, in the second embodiment of the present invention, the control method of the timer 200 can be selected by the selection register 200-1, and has the following features. 1. When the selection signal “1” is set in the selection register 200-1. The pulse output of the timer 200 can be started in synchronization with the interrupt control signal in terms of hardware. 2. When the selection signal “0” is set in the selection register 200-1. The CPU 1000 can start the pulse output of the timer 200 at an arbitrary timing.

[0040]

As described above, the timer of the present invention is
When performing pulse output control in synchronization with the interrupt signal, the register that controls the start and stop of the counter in the timer has a master / slave configuration, and is set in the control register on the master side in synchronization with the interrupt signal. By configuring the control information to be transferred to the control register on the slave side, it is possible to start counting up the counter in the timer by hardware in synchronization with the interrupt signal. This has the effect that the timer output can be generated at a high timing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional timer.

FIG. 4 is a diagram showing a pulse output waveform of a timer.

FIG. 5 is a diagram showing a start timing of a conventional timer.

FIG. 6 is a diagram showing a start timing of a timer of the present invention.

[Explanation of symbols]

 100-1 Counter 100-2-1 Control register 100-2-2 Control register 100-3 Comparison register 100-4 Comparison register 100-5 Comparator 100-6 Comparator 100-7 Match signal 100-8 Match signal 100- 9 SR flip-flop 300-1 Control register 1000 CPU 2000 Count clock 3000 Interrupt signal

Claims (2)

[Claims] 1. A counter that counts a count clock, and sets a coincidence timing between the count value of the counter and 2
Number of comparison registers, two comparators that compare the count value of the counter and the set values set in the two comparison registers, and output a match signal when they match, A timer output unit that outputs a controlled pulse, and a control unit that controls the start and stop of the counting operation of the counter, wherein the control unit is a master / slave of a master-side storage unit and a slave-side storage unit. The timer output section starts the counting operation of the counter in synchronization with the interrupt signal by transferring from the master side storage means to the slave side storage means in synchronization with an external interrupt signal. A timer device characterized by being output from a timer. 2. The timer device according to claim 1, further comprising a selection register for selecting a control method for starting and stopping the counting operation of the counter.