JP2794440B2 - PWM controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a PWM (Pull
se Width Modulation) control device.

[Conventional technology]

Conventionally, switching of control data to this kind of PWM control device has been performed at an arbitrary timing. This conventional technique will be described with reference to a block diagram of a PWM control device shown in FIG.

Reference numeral 1 denotes an up / down counter control block, in which a counter output value of an up / down counter (hereinafter referred to as a U / D counter) existing in this block is input to a data input terminal of a down counter of 3 through a signal bus line of 2. ing. The counter output value of the down counter 3 is input to a down count value determination circuit 5 through a bus line 4. Down count value judgment circuit 5
Outputs a duty control signal on signal line 6 according to the count value of down counter 3 and the data value on signal bus 25, and completes one cycle of pulse output on signal line 10; A load signal indicating the start of the next pulse signal formation is output.

The signal line 6 is connected to the waveform control signal input terminal of the PWM signal shaping circuit 7. Also, the signal line 10
These are connected to the LOAD signal input terminals of the blocks 1, 3, and 7, respectively. The signal output terminal of the PWM signal shaping circuit 7 is connected to the signal output terminal 9 through the signal line 8. The blocks 3, 5, and 7 are synchronized by the same clock, and a clock is input to each of the clock signal input terminals of the blocks 3, 5, and 7 through 23 signal lines.

Reference numeral 22 denotes a CPU bus line. The CPU outputs control data for blocks 1 and 5 output from the CPU to blocks 13 and 14 by controlling signals on address signal lines 14 and strobe lines 15. It is possible to set to. The signal output bus of the register 13 is connected to the control data input terminal of the block through signal buses 24 and 25, respectively.

 Next, the operation will be described.

At the same time as outputting the first control data on the signal bus 22, the CPU sends a control signal on lines 14 and 15 to set the data on the signal bus 22 to the register 13. The up / down counter control block 1 transmits this data to the bus line 24, and the down count value determination circuit 5
Ingest through. When output to the load signal line 10, the output value of the U / D counter of the block 1 is set to the data input terminal of the down counter circuit 3 at the falling edge of the load signal 10, and then the up / down counter control 1 Data values and signal lines on bus 24
The state of the 26 feedback signals is determined, and one of the three operations in which the output value of the U / D counter in the up / down counter control block 1 is increased by 1, decreased by 1, or not increased or decreased is selected and executed. Clock on line 23 is 0
Each time it rises from 1 to 1, the down counter 3 sets the output value of the U / D counter in the block of the up / down counter control 1 as its maximum value, and decreases the count output value of the down counter by 1 from that value. I do. Then, the down count value determination circuit 5 outputs the count output value of the down counter 3 through the bus line 4.
Take in every clock on line 23, line 25
Then, a signal for the required duty is created by comparing the data with the data from the corresponding data, and is output on the signal line 6. The PWM signal shaping circuit 7 generates a rectangular wave having a required duty using the signals on the lines 6, 10, and 23, and outputs the rectangular wave to the output terminal 9 through the signal line 8. Then, the down-count value judging circuit 5 outputs a load signal to the line 10 when the down-counter 3 further counts down and the count output value falls within a certain value range near zero.

The update of the set data of the register 13 in the conventional example is performed at a timing when there is no problem even if the clock stops or an error occurs in the output.

[Problems to be solved by the invention]

When trying to perform a soft start with the above-described PWM controller, it is necessary to frequently rewrite the data in the register 13, but no consideration is given to the timing of data transfer between the CPU and the PWM controller. If the data is frequently rewritten, the following problem occurs.

a. While the CPU is changing the control data, the PWM control circuit takes in the data, so that an abnormal pulse is output from the output terminal of the PWM control device, and there is a danger that the soft start may not be performed correctly.

b. Due to the abnormal pulse of a, the protection circuit of the power supply device is activated, and the power supply operation itself may be disabled.

In the past, the CPU circuit and the PWM control circuit were composed of separate ICs. However, if the CPU circuit and the PWM control circuit were to be built on a single-chip IC, the interface between the CPU circuit and the PWM control circuit would not work. If no consideration is given to the timing of data exchange, the expected value of the output pulse at the time of the operation test of the IC becomes undefined, making the test difficult.

The present invention has been made under such circumstances, and a PWM control device that does not malfunction even when data is frequently rewritten for a register that temporarily stores control data from a CPU. The purpose is to propose.

[Means for solving the problem]

In order to achieve the above object, the first invention of the present application employs a PWM
The control device is configured as in the following (1), and in the second invention of the present application, the PWM control device is configured as in the following (2).

(1) Provide the following components a, b, c, d, and e.

a. An up-down control unit having an up-down counter for determining a cycle of a pulse of a PWM output.

b. A down counter that loads the data of the up / down counter with a load signal and determines whether the PWM output is on or off.

c. A register for writing control data for the PWM output under the control of the CPU.

d. Synchronizing means for ensuring that the load signal always goes to H or L at the timing when the address signal of the register from the CPU goes from H to L or H to L.

e. means for prohibiting taking out of the control data from the register to the up / down control unit and the down count value judgment unit of the down counter when the CPU selects the address signal of the register.

(2) The following components a, b, c, and d are provided.

a. An up-down control unit having an up-down counter for determining a cycle of a pulse of a PWM output.

b. A down counter that loads the data of the up / down counter with a load signal and determines whether the PWM output is on or off.

c. A register for writing control data for the PWM output under the control of the CPU.

d. At a timing slightly preceding the load signal, the CPU determines whether or not the address signal of the register has been selected, and when it is determined that the address signal has been selected, the CPU determines from the register the up-down control unit and Means for prohibiting the control data from being taken out to the down-count value determination unit of the down counter.

[Action]

According to the above configurations (1) and (2), the operation of extracting the register data to the up / down control unit and the down counter value determination unit of the down counter during the rewriting of the control data of the register by the CPU is not performed. .

〔Example〕

 Hereinafter, the present invention will be described with reference to examples.

FIG. 1 is a block diagram of a PWM control device according to an embodiment of the first invention of the present application.

As compared with the conventional example shown in FIG. 8, the circuits 11a and 12 are added.
A description will be given below, and a description of a portion performing the same operation will be omitted.

12 synchronizes the CPU circuit with the PWM control circuit (register
13 is a latch circuit for prohibiting taking out of control data during rewriting of 13). The latch circuit latches the data set on the register 13 through the bus lines 18 and 19, and outputs the block 1 through the bus lines 20 and 21. And 5 are transmitted to the control data input terminals. Reference numeral 11a denotes a control circuit for the register 13 and the synchronization latch 12.
13 to output control signals. 10, 14, and 15 signal lines are connected to the control circuit 11a. Control circuit 11a
Captures the load signal from the signal line 10, the address signal from the signal line 14, the strobe signal from the signal line 15, and
Generate control signals to be output on 16,17. When the load signal is being output, the circuits 1, 5, and 7 are configured not to malfunction even if the data on 20, 21 and the data on the bus line 22 change. Except for the circuits 11a, 12, and 13, the description is omitted because it is the same as the conventional case. In particular, in order to explain the operation of the circuit portions 11a, 12, and 13, the internal circuit of 11a is specifically shown in FIG. .

The control circuit 11a includes a two-input AND gate circuit of 26 and 27 and an inverter circuit of 28, as shown in the drawing. The output terminal of the circuit 27 is connected to the signal line 17, and one of the input terminals is connected to the signal line 15, The other input terminal is connected to the signal line 14. The output terminal of the 2-input AND gate circuit 26 is a signal line.
The signal line 10 is input to one of the input terminals, the output terminal of the inverter 28 is connected to the other input terminal, and the input terminal of the inverter 28 is connected to the signal line 14.

Next, the operation will be described. FIG. 3 shows the time chart.

When the CPU writes data to register 13, register 1
Address signal for selecting address 3 is not shown in C
The signal is output from the PU to the signal line 14. The timing of the rising edge of the address signal and t _0. t ₀ strobe signal is output onto the signal line 15 at the timing of t ₂ after t _alpha from the register rewrite that is output on signal bus 22 at the timing of the sections or T ₁₄ from t ₀ to the address signal falls The data is taken into the register 13.

When the signal on the signal line 10 changes from 0 to 1 and from 1 to 0 in a section where 1 stands on the signal line 14, that is, within the range of T ₁₄ , one input terminal of the AND gate 26 is controlled by the inverter 28. Is 0, the content of the latch 12 remains unchanged from the original data A1.

Now, 1 next value of the signal line 15 is the timing of t ₂ which is in the range of T _14, 0 and becomes thereafter t _3, signal bus
Data A2 on 22 is set on register 13. afterwards
Signal on line 14 at the timing of T ₄ is changed to 0 from 1, further 1 stands on the signal line 10 at the timing of t ₅ after t _beta, A2 data on the register 13 at the timing of the latch Since the circuit 12 is in a through state, it is output onto the signal lines 20 and 21. Then, the signal on the signal line 10 changes from 1 to 0 at the timing of t ₆ from t ₅ to t _γ , and the data of A ₂ is latched by the synchronization latch 12. However, in the case of this data rewriting, the CPU and the PWM circuit are synchronized, and the LOAD signal on the signal line 10 is always at the timing when the signal on the signal line 14 changes from H to L or from L to H. L (H for negative logic circuits). Also, t
_α is always larger than t _γ , the timing when the signal line 14 is at L is larger than t _α ,
Above those of the timing is L is larger than t _α.

In this way, it is possible to prevent the PWM control device from malfunctioning by taking out the data of the register 13 to the up-down control unit 1 and the down-count value determination unit of the down counter 3 while the CPU rewrites the register 13.

 Next, an embodiment of the second invention of the present application will be described.

FIG. 4 is a block diagram of a PWM control device according to an embodiment of the second invention.

In this embodiment, as shown in FIG. 4, 24 signal lines are added as compared with the embodiment of FIG. Further, since the inside of the control circuit 11a has been changed, a portion performing an operation different from that of the embodiment of FIG. 1 will be described, and a description of the portion performing the same operation will be omitted.

FIG. 5 shows a specific circuit around the control circuit 11b. 2, the inverter circuit 28 is replaced by 29 D-type flip-flop (hereinafter abbreviated as DFF) circuits. That is, the signal line 14 is connected to the data input terminal D of the DFF circuit 29 and one input terminal of the AND gate of the DFF circuit 29, the signal line 24 is connected to the clock input terminal of the DFF circuit 29, and the output is two-input AND. The gate 26 is connected to one input terminal, and the signal line 10 is connected to the other signal line. The other end of the signal line 24 is connected to a timing signal output terminal of the down-count value determination circuit 5.

In this embodiment, unlike the embodiment of FIG. 1, the address signal and the load signal are not synchronized.

Next, the operation will be described. The method of generating the PWM output signal is the same as the conventional example or the embodiment of FIG. 1, and the load signal is used as a reference. Usually, the length of one cycle of the pulse of the PWM output signal corresponds to the time interval between the output of two load signals that are continuously output. That is, the count value of the U / D counter in the block 1 is set in the down counter 3 by the load signal, the value is down-counted by the clock, and the down-count value determination circuit 5 down-counts to the count value to output the load signal. It determines that the counter has counted down, generates a load signal, and repeats the cycle of loading the U / D count value of the up / down counter into the down counter again. In this PWM controller, the load signal is output for two clocks of the basic clock. When the load signal is being output, the circuits in blocks 1, 5, and 7 are connected to signal lines 20 and 21. It does not malfunction even if the data changes. Now, when the load signal is output on the signal line 10 when the down counter value counts down to 1 and 0, and when the value of the U / D counter in the up / down control block 1 at that timing is X, the load signal becomes When it is exhausted, X is loaded into the down counter 3 at the timing.

That is, the time when the X value is counted down to 0 by the down counter 3 is one cycle of the PWM signal. now,
It is assumed that the time during which the down-counter 3 counts down to X is equal to or greater than five times the time during which the load signal is output. When the down-count value has a value of 2,1, that is, the down-count value determination circuit 5 operates such that 1 is output on the signal line 24 at the same timing as the load signal. (See FIG. 7).

Now, the time when the address signal 14 becomes 1 becomes 1 when the load signal becomes 1.
It is assumed that the time when 14 is 0 is at least twice as long as when 14 is 1. The time t _alpha from time t ₀ to 1 stand 14 until time t ₂ when 1 goes to 15 the load signal is at least twice the time when the 1. The time during which the load signal is output is represented by _tγ .

When 1 is set at 14 when the signal on the signal line 24 changes from 0 to 1 (see FIG. 6C), when 1 is set at 14 signal lines in the embodiment of FIG. , 10 operate in the same way as when the load signal on the signal line changes from 0 to 1. That is, the operation is the same as that of the previous embodiment except that the operation of turning the 1 signal on the signal line 14 into the DFF 29 and setting one input terminal of the AND gate 26 to 0 is performed. Similarly, signal lines
When the signal on 24 changes from 0 to 1, 0
(See FIG. 6 (a)), the operation equivalent to that when the load signal on the signal line 10 changes from 0 to 1 when the signal line 14 is 0 in the previous embodiment. do.
That is, since the signal on the signal line 14 is 0,
When the above signal changes from 0 to 1, DFF 29 remains at 1, and the same operation as in the previous embodiment is performed except that one input terminal of the AND gate 26 becomes 1. However, in this embodiment, the timing at which the signal on the signal line 24 changes from 0 to 1 and the timing at which the signal on the signal line 14 changes from 0 to 1, or from 1 to 0 are completely asynchronous. Even if the operation occurs, the circuit does not malfunction.
This operation will be described below.

Simultaneous signal change on signal lines 14 and 24 means DF
At the timing when the clock of F29 changes from 0 to 1, the signal of the D input terminal is equivalent to an undefined state, and its output becomes 1 or 0, but it is undefined.
If the data at the output of DFF29 is fixed from the time when the above signal changes from 0 to 1 to the time when the line 10 changes from 0 to 1, the subsequent operation itself is unique by the value of the output of DFF29. Is determined. Now, since t _α is larger than 2 × t _γ , as shown in FIG. 6B, the signals on the signal lines 14 and 24 rise simultaneously, and even if the signal on the signal line 14 is determined to be 1, The time when the load signal 10 falls is the signal line
Since the signal on line 15 is configured to be before rising from 0 to 1, at the timing when the signal on signal line 15 rises from 0 to 1, the latch 12 is in the latch state,
No malfunction occurs due to rewriting of data by the CPU. Of course, when the signal on the signal line 14 is determined to be 0, the data in the latch 12 is not changed and no problem occurs.

Similarly, because the time signal on the signal line 14 is 0 is larger than T _14, as a time chart of the timing of FIG. 6 (d), the timing at which the signal on the signal line 24 rises from 0 to 1 When the signal on the signal line 14 falls from 1 to 0 at the same time, even if the signal on the signal line 14 is determined to be 1 and DFF29, if the signal on the signal line 10 is 1, the signal line 16
Since the above signal does not become 1 immediately, the data in the latch 12 is not changed at all and does not cause any problem. Also, signal line
When the signal on the signal 14 is determined to be 0, the data on the register 13 is latched by the latch 12 under the condition that the data on the signal line 14 is 0, and no problem occurs.

As described above, in the present embodiment, the CPU determines whether or not the address signal of the register has been selected at a timing immediately preceding the load signal (before the settling time of the DFF or more), thereby determining the address signal. The function of preventing malfunction of the PWM control device similar to the embodiment of FIG. 1 can be obtained without synchronizing the load signals.

〔The invention's effect〕

As described above, according to the first and second aspects of the present invention, a. Even if the CPU switches control data at an arbitrary timing, control can be performed so that no abnormality occurs in the PWM output. .

b. Since the above item a becomes possible, it becomes easy to control the soft start of the switching power supply controlled by using the PWM output signal, which requires the control data to be frequently switched and controlled.

c. When the CPU and the PWM output signal generation circuit are configured on the same IC, the expected value of the output value is uniquely determined, and the circuit test of the IC becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the first invention of the present application, and FIG.
FIG. 3 is a connection diagram of the control circuit of the embodiment, FIG. 3 is a timing chart showing the operation of the control circuit, and FIG.
FIG. 5 is a connection diagram of the control circuit of the embodiment, FIG. 6 is a timing chart showing the operation of the control circuit, and FIG. 7 is a timing chart showing the operation of the second invention. FIG. 8 is a block diagram of a conventional example. 1 ... Up / down counter control block 2 ... Down counter 5 ... Down count value judgment circuit 11a, 11b ... Control circuit 12 ... Synchronization latch 13 ... Register 26,27 ... And gate 28 ... Inverter 29 ...... D-type flip-flop (DFF)

Claims (2)

(57) [Claims] 1. A PWM control device comprising the following components a, b, c, d, and e. a. An up-down control unit having an up-down counter for determining a cycle of a pulse of a PWM output. b. A down counter that loads the data of the up / down counter with a load signal and determines whether the PWM output is on or off. c. A register for writing control data for the PWM output under the control of the CPU. d. Synchronizing means for ensuring that the word signal always becomes H or L at the timing when the address signal of the register from the CPU changes from H to L or from L to H. e. means for prohibiting taking out of the control data from the register to the up / down control unit and the down count value judgment unit of the down counter when the CPU selects the address signal of the register. 2. A PWM control device comprising the following components a, b, c, d. a. An up-down control unit having an up-down counter for determining a cycle of a pulse of a PWM output. b. A down counter that loads the data of the up / down counter with a load signal and determines whether the PWM output is on or off. c. A register for writing control data for the PWM output under the control of the CPU. d. At timing slightly preceding the above load signal,
The CPU determines whether or not the address signal of the register is selected, and when it is determined that the address signal is selected, the control data is transferred from the register to the up / down control unit and the down count value determination unit of the down counter. Means to prohibit taking out.