JPH04196723A - Pwm controller - Google Patents

Abstract

PURPOSE:To prevent a malfunction at a high speed clock by forming a PWM output signal with a 2nd control data extracted from a latch means in response to a data set signal, a counting output data from a down--counter and the data set signal. CONSTITUTION:A data set signal line 13 is connected to the control signal input terminal of a waveform shaping circuit 5, and a part of signals of a data latch 6 is inputted to the circuit 5 through a signal line 14. Thus, the circuit 5 generates a PWM output in response to the signal on signal line 11-15 and outputs the PWM signal to a PWM signal output terminal 17 through a signal line 16. A signal line 13 is connected to a down-counter 3, an up-down control circuit 1 and a data set signal input terminal of the data latch circuit 6, and the circuit 6 receives a control data for a CPU 7 via a signal bus 18 and transmits it to the circuits 5, 1 through data buses 14, 19. Thus, no malfunction is caused at a high speed clock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PWM control device suitable for controlling switching power supplies and the like.

[Conventional technology]

Traditionally, this type of PWM control device has been described in the National Technical Report.
Report Vol 24. No.l.Feb.19
78 AN shown on pages 154 to 165)
6510 (which was an analog system).

Problems to be Solved by the Invention C] In the conventional example, control is performed using an analog method, and therefore control by a CPU, which is a digital method, is difficult. In particular, it is difficult to perform data conversion and synchronization in the interface section that exchanges data, and the circuit size becomes large.

On the other hand, the control accuracy itself in analog PIM circuits is good, and in order to obtain the same control accuracy with digital circuits, the clock frequency must be set to a high frequency such as 16 MHz, and the design of digital PWM circuits is based on this. It was necessary to create a system that would not cause malfunctions even with such a high-speed clock, and would be easy to control.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a digital PWM control device that is free from erroneous operation using a high-speed clock.

[Means for Solving the Problems] The present invention includes a latch unit that latches control data related to a PWM ill force signal, an up/down counter that determines the period of the PWM output signal, and a latch unit that latches control data related to a PWM ill force signal, an up/down counter that determines the period of the PWM output signal, and A down counter in which the count 6 data of the up/down counter is set in response to the supplied data set signal, and first control data retrieved from the latch means in response to the data set signal, up/down control means for controlling a down counter; second control data taken out from the latch means in response to the data set signal; count output data of the down counter; and a PWM output signal based on the data set signal. a waveform forming means for forming;
The apparatus is equipped with eight signal product circuits for detecting the division of one period of the PWM output signal and for detecting an asynchronous signal from the outside.

[For production]

According to the present invention, by sharing the PWM drawing device path, it is possible to simplify the device and eliminate delays in circuit operation.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

Figure 2 is a lock diagram of a PWM control device according to a first embodiment of the present invention. In the figure, reference numeral 1 indicates an up-down cross section circuit, which is a circuit that controls the count up and count down of an up/down counter (hereinafter referred to as a 1/D counter) 2. The clock output terminal of the up/down control circuit 1 is connected to the Ll/D down counter lock input terminal through a signal line 20. In addition, the U/D system terminal of the picture design circuit 1 is connected through the signal line 10.
It is connected to the IJ/Dtlyll@ signal input terminal of the U/D counter 2.

Feedback for PWM control (FEED BAC
K) The signal terminal 8 is connected to the feedback signal input terminal of the up-down control circuit 1 through a signal line 9. The count value of the U/D counter 2 is connected to the data input terminal of the down counter 3 and the U/D count data input terminal of the waveform shaping circuit 5 through a pass line 11. A count value data output terminal of the down counter 3 is connected to a signal detection circuit 21 and a down counter data input terminal of the waveform shaping circuit 5 through a pass line 12.

The count value determination circuit 4a outputs a data set signal on the signal line 13 in accordance with the data from the signal detection circuit 21, indicating the timing at which one cycle of pulse output of the PWM signal is completed and the next pulse signal formation starts. This circuit has the function of The data set signal line 13 is connected to a control signal input terminal of the waveform shaping circuit 5. A part of the signal from the data latch 6 is further input to the waveform shaping circuit 5 through a signal line i4. Therefore, depending on the signal on the signal line 11.12.13.14.15, the waveform shaping circuit 5 generates a PWM output, and the signal line 1
Eight PWM signals are applied to the terminal I7 via the terminal I7.

The signal line 13 is connected to data set signal input terminals of the down counter 3, the up/down control circuit 1, and the data latch circuit 6. Data latch circuit 6 is CPU7
control data is received through the signal bus 18 and transmitted to the waveform shaping circuit 5 and the up/down control circuit 1 through the data bus 14.19. 7-1 is a line through which a write signal for the CPU 7 to write information to the data latch circuit 6 is transmitted.

The clock signal that provides the timing reference for the entire circuit is
Down counter 3, signal detection circuit 21 . It is connected to the clock signal input terminals of the count value determination circuit 4a and the waveform shaping circuit 5.

Next, the operation of the first embodiment shown in FIG. 2 will be explained.

The CPU 7 outputs control data for controlling the present PWM control device onto the signal bus 18, and at the same time outputs control data to the signal line 7--
1, and data for controlling the PWM control device is set on the data latch circuit 6.

However, the data is output onto the signal lines 14 and 19 at the timing of the rise of the data set signal on the data set signal line 13. Here, the value of "1" on the signal line 13 is assumed to be a data set signal.

Now, when "1" is set on the signal line 13, the waveform shaping circuit 5 is set, and P is output through the signal line 16.
It operates so that "1" is output to the WM signal output terminal 17. Further, the output value of the U/D counter 2 is set in the down counter 3. The up/down control circuit 1 operates in synchronization with the rising and falling edges of the data set signal (load signal) on the line 13. That is, the up/down control circuit 1 outputs the signal ((
determine the state of the first control data), determine the data to be output on the signal line lo, and output the data set signal (load signal).
signal line 20 in synchronization with the falling timing of
The clock should be output on the signal line 2o to increase or decrease the count output value of the U/D counter 2 by 1, or to stop the U/D counting operation of the up/down counter (count up or down on the signal line 2o). It operates so as not to output the clock for.

The down counter 3 takes the count output value of the U/D counter 2 as its maximum value and converts the count value of the down counter 3 from that value into a clock signal of "1" on the signal line 15.
The waveform shaping circuit S takes in the count output value of the down counter 3 through the signal line 12, and inputs the control data (number 1) on the data bus 14. 2 control data) and the falling edge of the clock signal on signal line 15. If the two values match, signal line 1
By changing the data outputted to the PWM signal output terminal 17 from "1" to "0" through 6, duty control of the signal outputted to the output terminal 17 is performed.

The waveform shaping circuit 5 also captures the data on the signal line 11 at the falling edge of the signal on the signal line 13,
The value is compared in magnitude with the 8-force operation control data given on the data bus 14, and when the data on the signal line 11 is smaller than the output operation control data given on the signal line 14, the PWM signal output terminal 17 is simply "1", the PWM signal a stops, and the PWM signal is activated only when it is large.
The signal is turned on.

All the flip-flops constituting the down counter 3 operate in synchronization with the fall of the clock signal applied to the signal line 15, and when "1" is on the signal line I3, the operation of the down counter 3 is disabled. Stop and pass line 1
The count output value of 2 is changed to data on the signal bus 11 and connected as is.

The operating state when the data on the signal line 11 is greater than the output operation control data applied on the signal line 14 will now be described.

The count value determination circuit 4a inputs the dollar data of the signal detection circuit 21 through the signal line 22, determines it in synchronization with the falling edge of the clock signal on the line 15, and determines whether the value on the signal line 13 is a predetermined value near zero. Output the dataset signal to.

Next, the operation of the signal detection circuit 21 will be explained with reference to the detailed diagram of the signal detection circuit shown in FIG. In the reset state, the data on pass line 12 is changed to the data on signal bus 11, and the LOAD signal on line 13 becomes "1".

Then, in response to the fall of the clock signal on the line 15, the output "0" of the NOR gate 26 is output to the signal line 22.
is output to the line 13 by the count value judgment circuit 4a.
The upper LOAD signal becomes "0".

The output of the OR gate 24 is "1" when data is set on the pass line 12, and the signal line 28 is also "1".
1", so if the TIM signal on the line 23 is "1", the output of the NOR gate 26 is held at "0". Therefore, the down counter 3 sets all the data on the data bus 12 to "0". ” or the TIM signal on line 23 becomes “O”, AND gate 2
When the output of the NOR gate 26 becomes "0", the output of the NOR gate 26 becomes "1", and in response to the fall of the clock signal on the line 15, "1" is set on the signal line 22.

As a result 1, the LOAD signal on line 13 becomes "1" and the data on data bus 12 is changed to the data on signal bus 11, returning to the reset state. Therefore, the TIM signal on line 23 becomes "1". The data on the signal line 22 can be set to "1" regardless of the data on the data bus 12. Therefore, in this embodiment, the output of the PWM output terminal 17 is set to "1" during the "1" period.

It is possible to change the period of "0" at the same time, making it possible to perform PWM control of complex circuits.

FIG. 3 is a block diagram showing a second embodiment. Third
The embodiment shown in the figure is actually used in a power supply circuit, and one or more 8
Resistors R1 and R2 from one of the power supply circuits that obtain power.
The signal is detected and compared with the data from the CPU 7 to obtain a FEED BACK (feedback) signal. Further, the zero-crossing point of the falling edge of the waveform of the output signal 24 (shown in FIG. 4) from the transformer T1 is detected and set as the TIM signal on the line 23. At the timing of this TIM signal, the transistor Tri is turned on, and the transistor Tr+ is also turned on. Therefore, if the transistor Tr+ was turned on while voltage remained in the transformer T1, a large current would flow into the transistor Tr+ itself, potentially destroying the transistor Tr+, but now the voltage of the transformer T has become completely zero. By detecting this and operating the transistor Tr+, a large current will not flow into the transistor Tri.

FIG. 6 is a block diagram showing the third embodiment. Third
Regarding this embodiment, explanation of the parts common to the first embodiment will be omitted, and only the different parts will be explained.

Compared to the first embodiment, latch circuit (flag) 6-1.
Inverter circuit 6-4. An AND gate circuit 6-5 is added.

Data bus 1 is connected to data input terminal I of latch circuit 6-1.
A signal line 6-2 is connected to the latch signal input terminal, which is connected to a latch control signal output terminal of the CPU 7. The Q output terminal of the latch circuit 6-1 is connected to the input terminal of the inverter 6-4, the reset input terminal of the data latch circuit 6, and the flag control signal input terminal of the count value determination circuit 4b through the signal line 6-3. There is. The output terminal of the inverter 6-4 is connected to one input terminal of the AND gate 6-5, and the other input terminal of the AND gate 6-5 is connected to the PWM signal output of the waveform shaping circuit 5 via the signal line 16. connected to the terminal. The output terminal of the AND gate 6-5 is connected to the PWM signal specific power terminal 17.

Next, the count value determination circuit 4b will be explained with reference to FIG. Here, the block 4b surrounded by the broken line is
Count value detection 8 circuits 4-1. OR circuit 4-2. It is composed of a D-type flip-flop circuit 4-3.

The signal line 22 is connected to the input terminal of the count value detection circuit 4-1, and the output terminal of the count value detection circuit 4-1 is connected to one input terminal of the OR gate 4-2 through the signal line 4-4. A signal line 6-3 is connected to the other input terminal of the OR gate 4-2, and the output terminal of the OR gate 4-2 is connected to the D input terminal of the D-type flip 70 tube 4-3 through the signal line 4-5. has been done. The Ql output of the D-type flip-flop 4-3 is connected to the signal line 13, and the clock input terminal is connected to the signal line 15. However, the D type flip-flop 4-3 is a flip-flop of a type that takes in data on the D input terminal to the Q output terminal at the falling edge of the signal on the signal line 15.

Next, the operation of this embodiment will be explained. Common parts with the first embodiment will be omitted, and only the different parts will be described. The latch circuit 6-1 is a flag for controlling the system, and is a flag for controlling the CPU.
7 outputs a control signal onto the signal line 6-2 and the data bus 18, and outputs a set signal to the latch circuit 6-1, thereby controlling the Q pressure of the latch circuit 6-1. . When the Q output of the latch circuit 6-1 is “1”, the data on the signal line 6-3 is “1”.
”, and the AND gate 6-
Since the inverted signal “0” is added to one input of P
WM output terminal 17 is fixed at "0".

At this time, "1" is applied to the D input terminals of the D type flip-flops 4-3 through the OR gate 4-2, so the signal is the falling edge of the signal on the signal line 15.
A value of "1" is output to the Q output terminal. When "1" is output to the Q output terminal of the D-type flip-flop 4-3, the data set signal on the signal line 13 continues to be "1°" and the operation of the PWM circuit is stopped.

The count value detection circuit 4-1 has the functions of detecting the data set signal on the signal line 13 and determining the count value of the down counter 3, so it outputs "1" to the signal line 6-3.
” is added, the count value detection circuit 4-1
The output terminal of is “0”. For this reason, C:PU
T sets the set data of the Q output of the latch circuit 6-1 to “L”
When the signal is changed from "O" to "O", the signal on the signal line 6-3 changes from "1" to "0", and the signal on the signal line 4-5 also changes from "1" to "0". Furthermore, when the signal line 6-3 becomes "0", the signal on the signal line 16 can be output as is to the output terminal of the AND gate 6-5.Then, the signal on the signal line 4-5 becomes "1". ” to “0”, the signal on signal line 15 changes from “1” to “0”.
”, flip-flop 4-3
The Q output data changes from "1" to "0", and the subsequent operation is the same as in the conventional example.

Note that the data latch circuit 6 has a signal line 6-3 of “1”.
”, the data on the bus 14.19 is in a state where it can be changed to a confession by a command from the CPU 7. Even if the output data of the data latch circuit 6 changes, “1” is not displayed on the signal line 13. In the range where is output, the circuit operation is stopped and no malfunction occurs.

Since this embodiment operates as described above, the CPU circuit and P
Even if the WM circuit and the WM circuit operate asynchronously, the CP
The U circuit makes it possible to control the operation of the PWM circuit without malfunction.

Note that the latch circuit 6-1 can be easily replaced with a D flip-flop.

K1 Yutaka A Next, a fourth embodiment of the present invention will be described.

FIG. 7 is a block diagram showing a PWM control device according to a fourth embodiment. Only the points different from the third embodiment described above will be explained, and the explanation of the others will be omitted.

The fourth embodiment differs from the second embodiment in that the signal line 6-3 is connected to the reset terminal of the U/D counter 2. The U/D counter 2 has a circuit configuration in which when it is reset, it is reset to a value such that the duty ratio of the PWM signal outputted to the line 16 is minimized.

Next, the operation of this embodiment will be explained. The difference from the second embodiment is that when the CPU 7 sets the Q output terminal of the latch circuit 6-1 to "1", it simultaneously controls the output terminal of the PWM signal and resets the U/D counter 2. It will be done. As a result, P can be easily controlled by the CPU 7.
It becomes possible to restart switching power supply voltage control while initializing the PWM output signal output to the WM signal output terminal 17 and performing new soft start control.

The third and fourth embodiments described above can also be applied to the second embodiment instead of the first embodiment.

[Effects of the Invention] As explained above, according to the present invention, by making it possible to control the PWM output signal using an external timing signal, it is possible to cope with the increasing complexity of controlled objects and increasing the precision of control. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a signal detection circuit in a first embodiment of the present invention, FIG. 2 is a block diagram showing the entire first embodiment, and FIG. 3 is a block diagram showing a second embodiment. , Figure 4 is the second
FIG. 5 is a diagram showing the count value determination circuit used in the third and fourth embodiments. FIG. 6 is a block diagram showing the third embodiment. FIG. is the fourth
It is a block diagram showing an example of. ■...up/down control circuit, 2...U/D' (up/down) counter, 3
... Down counter, 5... Waveform shaping circuit, 7... CPU. 8...FEED BACK (feedback) signal input terminal, 17...PWM output terminal, 21...signal detection circuit, 23...timing signal line. 2nd Pig SL Example 1 = Five-toned various reviews of Ii Ui modified loco Fig. 4 Fig. 5

Claims (1)

[Scope of Claims] 1) A latch unit that latches control data related to a PWM output signal, an up/down counter that determines the period of the PWM output signal, and a data set signal that is supplied when its own count value is near zero. a down counter to which count output data of the up/down counter is set in response to the data set signal; and an up/down counter that controls the up/down counter by first control data taken out from the latch means in response to the data set signal. down control means, second control data taken out from the latch means in response to the data set signal, count output data of the down counter, and PW by the data set signal.
A PWM control device comprising: a waveform forming means for forming an M output signal; and a signal detection circuit for detecting a break in one period of the PWM output signal and detecting an asynchronous signal from the outside. 2) The PWM control device according to claim 1, wherein in the signal detection circuit, one flip-flop is used to temporarily hold both detection signals. 3) The PWM control device according to claim 2, wherein the detection signal inverts the PWM signal after a delay of at least one clock of a clock that drives the post-detection PWM signal generation circuit. 4) The PWM control device according to claim 3, wherein after the detection signal inverts the PWM signal, stored information in a flip-flop of the detection circuit is reset.