JP3221109B2 - Multiprocessor system and TOD synchronization control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention, in a multiprocessor system, TOD synchronization control in respect of the inter-CPU, particularly in TOD synchronization process to prevent malfunction due to interference between the CPU, accurate TOD synchronization process and which make it possible to quickly perform, but about the TOD synchronization process.

2. Description of the Related Art In recent years, with the diversification of data processing in a data processing system and an increase in the amount of processing, the construction of a multiprocessor system, particularly, a tightly- coupled multiprocessor system sharing a main storage device has become active. .

When such a multiprocessor system is executing online processing, each of the central processing units
Since the TOD clock in (CPU) has a converted value of real time, it must have the same value, and if the value is different,
It may cause malfunction as a system.

Therefore, it is necessary to correctly adjust the TOD clock in each central processing unit (CPU). However, if the synchronization processing for correctly adjusting the TOD clock takes a long time, it takes time for the system to start up or a failure may occur. Because of the time-consuming problem of time recovery, especially in data processing systems that perform real-time processing, TO
D A synchronization control method that can synchronize clocks is required.

[0005]

2. Description of the Related Art FIG. 6 is a diagram for explaining a multiprocessor system. FIG. 6 (a) shows an example of the overall configuration of the system, and FIG. 6 (b) shows a TOD clock. 7,
FIG. 8 is a diagram showing a conventional TOD synchronization setting process.
FIG. 7 shows a case of normal operation, and FIG. 8 shows a case of abnormal operation.

A so-called TOD (Time Of Day)
The clock indicates a consistent elapsed time for displaying the date and time. For example, the clock has a format shown in FIG.
It consists of a binary counter.

[0007] The TOD clock is, for example, every 1 μsec.
It is increased by adding "1" to bit 51 of (b). The value of the TOD clock can be set by a SETCLOCK (SCK) instruction.

For example, a main storage device as shown in FIG.
In the case of a tightly-coupled multiprocessor system sharing two, the CPUs (CPU) (0) to CPU (n) may be hereinafter referred to as each central processing unit #. ｝ 1 is independently TOD clock T (0)
Owns ~ T (n) 10.

These TOD clocks T (0) to T (n) 10 are:
As described above, since the real-time data processing system has a real-time conversion value, all CPUs (0) to CP
U (n) 1 must have the same value, and different values may cause malfunction of the system.

For this reason, for example, when the system is started, all CPUs are set in advance by synchronous setting processing of the TOD clock.
(0) -Synchronization setting processing is performed so that the TOD clocks 10 of the CPU (n) 1 have the same value.

This TOD synchronization setting process is performed, for example, as shown in FIG.
Is performed as shown in FIG. First, one central processing unit {CPU (0)} 1 of the multiprocessor system becomes the main, and instructs the other CPUs (1) to CPU (n) 1 to start synchronization setting. {See processing step 230 in FIG. 7} At this time, for example, the TOD clock (TO) 10 of CPU (0) 1 is t
It is assumed to indicate seconds. Other CPU (1) to CPU (n) 1
Turns on a so-called STOP bit provided in a control register (not shown) in order to initialize the TOD clock 10 according to the above instruction. {See processing step 231 in FIG. 7} Then, as is well known, for example, (t + 1) second
When the above-described SCK instruction is executed by designating the OD clock 10, the value after (t + 1) seconds is set in the TOD clock 10 of each of the CPUs (0) to (n) 1, and the TOD clock 10 stops. {Refer to processing step 232 in FIG. 7} Then, when only the TOD clock (TO) 10 of the main CPU (0) 1 operates and the TOD clock (T0) 10 carries one second, ie, for example, t When switching from the second level to (t + 1) seconds, a synchronization signal is issued to the other CPU (1) to CPU (n) 1 to start the counting operation of the other TOD clocks (T1) to (Tn) 10. .

Thus, all the TOD clocks (T0) to (T0)
n) All 10 start operating at exactly the value of (t + 1) seconds and are synchronized. This synchronization signal is transmitted via the control bus 3a constituting the common bus 3 in the multiprocessor system of FIG.
(0) to CPU (n) 1 constantly monitor the control bus 3a, and upon detecting the synchronization signal, their TOD clocks (T1) to (Tn) 10 immediately start counting. It is configured as follows. << Refer to processing steps 233 and 234 in FIG.

[0013]

FIG. 8 is a diagram for explaining a problem with the conventional method. According to the above conventional synchronization control method, for example, there is no problem in a multiprocessor system having two CPUs, but three or more CPUs
In the system having the above, there is a problem that a correct synchronization cannot be obtained due to interference between CPUs other than the main CPU which starts the synchronization processing.

That is, generally, the hardware related to the TOD clock 10 is used.
As described above, when the STOP bit is set and the TOD value is set by the SCK instruction as described above, the synchronization signal is transmitted to the control bus 3a when the TOD clock of one of the other CPUs 1 is carried by one second. To each CPU 1
Since the TOD clocks (T0) to (Tn) 10 have a structure in which the counting operation is started by the synchronization signal, they start operating at the same time.

Therefore, for example, as shown in FIG.
Between the time when U (2) 1 turns on the STOP bit and the time when the SCK instruction is executed, the TOD clock (T2) of CPU (2) 1
10 happens to be a one-second carry ｛T of CPU (2) 1
Depending on the count status of the OD clock (T2) 10, the CPU
(2) The carry of one second may occur between 1 when the STOP bit is turned on and when the SCK instruction is executed (for example, at the timing when the STOP bit is turned on). Then, by the synchronization signal, C
The TOD clock (T1) 10 of PU (1) 1 will start.

For this reason, after completion of the conventional synchronization period setting process, the TOD clocks 10 of all the CPUs (0) to (n) 1 are read out to confirm whether or not synchronization has been correctly achieved. The above process had to be repeated many times. In particular, as the number of CPUs 1 increases, the above-mentioned interference occurs more frequently, and there is a problem that it takes time to start up the system.

As a similar technique for solving the above problem,
JP-A-61-13364 discloses a "TOD synchronization setting processing method" and JP-A-62-49555 discloses a "timing synchronization device for a multiprocessor system".

Japanese Patent Application Laid-Open No. 61-13364 discloses "TOD synchronization setting processing method".
D One of the central processing units (a specific central processing unit) that starts the synchronous processing sets information for instructing the TOD reset in a predetermined area of the main memory, and resets the TOD reset in all the other central processing units. When the completion is detected, all other central processing units are instructed to start the synchronization setting.
After setting the initial value instructed by the central processing unit that activates the TOD synchronization processing, the central processing unit that activates the TOD synchronization processing uses a synchronization signal one second higher than that of the central processing unit to activate all the central processing units from the initial value. TOD starts counting ", but one at the TOD of a particular central processing unit.
The timing of the carry of the second and the T in other central processing units
Since the relationship between the timing of setting the initial value to the OD and the timing is unclear, there remains a problem that accurate synchronization cannot be guaranteed.

Japanese Patent Application Laid-Open No. Sho 62-49555, entitled "Timekeeping Synchronous Device of Multiprocessor System" describes "in a multiprocessor system, the first time value is set in the timekeeping mechanism of one processing device and activated. The second time value after the first time is set in the time mechanisms of all the other processing devices, and the time mechanism activated by the one processing device indicates the second time value. When the timing mechanism of all the other processing devices is activated, the mechanism that synchronizes when the timing mechanism of the specific processing device changes from the first time value to the second time value is: JP-A-61-13364, `` TO
D synchronization setting processing method ", and the relationship between the timing of the synchronization signal from the specific processing device and the processing timing of setting a second time value in each processing device is unclear. However, there remains a problem that accurate synchronization cannot be guaranteed.

In view of the above-mentioned conventional disadvantages, the present invention prevents interference between CPUs when synchronizing TODs between CPUs in a multiprocessor system, without synchronizing TODs by trial and error, and , The synchronization process is performed irrespective of the timing operation of a specific CPU,
The synchronization setting of the OD clock can be accurately performed. TOD
It is an object of the present invention to provide a synchronization control method.

[0021]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 1 (a) shows an example of the entire configuration, and FIG. 1 (b) shows a TOD timepiece. 2 shows a configuration example of a count suppression and start instruction circuit. The above problem is solved by a TOD synchronization control method configured as follows.

(1) A plurality of TOD clocks 10 each provided
Multiprocessor system having a central processing unit 1
There are, privileges a particular central processing unit performs TOD synchronization
And synchronization authority acquisition means for acquiring, the central processing unit Bei
Instruction to suppress the counting operation of the TOD clock 10
Signals and signals to start counting
To obtain TOD count control signal means and synchronization authority
The new central processing unit stores the new TO in a predetermined area of the main storage device.
T to set D value and interrupt other central processing unit
OD synchronization means , while receiving interruption of TOD synchronization
The central processing unit stops the instruction execution operation and mainly describes the stopped state.
Means for setting display in a predetermined area of the storage device, and synchronization authority
The acquired central processing unit is stopped in other central processing units
Is detected by a predetermined area of the main storage device, and TO
Counting of TOD clock via D count control signal means
TOD clock that sends out signal a instructing operation inhibition
Und suppression means and suppression of the count operation of the TOD clock
The central processing unit that detects the command signal reads the new TOD value.
Set to your own TOD clock
TOD setting means to set display on the area and acquire synchronization authority
The obtained central processing unit has completed setting all TOD values.
Is detected, and T is detected via the TOD count control signal means.
Sends signal b instructing the start of the counting operation of the OD clock
And means for starting TOD counting.
You.

(2) The multiprocessor system according to claim 1
Stem, to suppress the count operation of the TOD clock 10
Timing of receiving the instruction signal a and the TOD clock
Receives signal b instructing start of 10 count operation
Timing is the count timing of each TOD clock 10
(EN1M) and a certain time, for example, duty 50
Configured to have timing shifted by time (EN1MH)
It is characterized by doing .

(3) The multiprocessor system according to claim 1
A stem, wherein the TOD count control signal means comprises:
With a circuit configuration in which signal lines from the central processing unit are dot-ORed
There is a feature .

FIGS. 3 and 4 show the flow of the synchronization process of the present invention.
Shown in the figure . (4) Multiple central processing units each equipped with a TOD clock
TOD Synchronization in Multiprocessor System
Control method in which a specific central processing unit performs TOD synchronization
Synchronization Authorization Acquisition Stage ( 200)
And the central processing unit that has acquired the synchronization authority is the main storage device.
A new TOD value is set in a predetermined area of (201), and another central processing is performed.
An interrupt to the management device (202) TOD and synchronization phase, T
The central processing unit that received the OD synchronization interrupt executes the instruction
Stops the operation and displays the stopped state in a predetermined area of the main storage device.
(220) and the central processing that has acquired the synchronization authority.
The main processing unit determines that another central processing unit is in the stopped state.
It is detected by a predetermined area of the storage device (204), and each central processing unit is detected.
Instruction to suppress the count operation of the TOD clock provided in the device
Signal to start counting and a signal to instruct
TOD clock transmitted via TOD count control signal line
TOD that sends out a signal instructing suppression of the count operation
Clock count suppression stage (205) , TOD clock count
A central processing unit that detects a signal instructing operation suppression
Read the TOD value and set it to your TOD clock (222, 2
07) TOD setting to display setting completion in a predetermined area
Steps (223,208) and the central processing unit that has acquired the synchronization authority
Detects that all the TOD values have been set (209)
Of the TOD clock via the TOD count control signal line
Sends a signal instructing the start of the counting operation, and each TOD
TOD count start stage to start counting (210,224)
Are sequentially processed to synchronize the TOD.

[0026]

That is, any central processing unit (here, CPU
(0)), for example, by a test & set instruction,
Check "0" in a predetermined area of the main storage device, and check that area.
Is set to “1” to obtain TOD synchronization authority
Then, the new TOD value is stored in another predetermined area of the main storage device.
After that, each central processing unit (hereinafter referred to as CPU (1) to (n))
To interrupt the execution of the instruction,
Instruction execution is stopped at each of the interrupted CPUs (1) to (n).
Performs processing and sends a notification of completion to a predetermined area of the main storage device.
Set to .

The CPU (0) having acquired the TOD synchronization authority
Looking at a predetermined area of the main storage, all CPUs (1) to
Confirm that (n) has stopped executing the instruction, and
An instruction signal for suppressing the counting operation of the total is transmitted .

When this TOD count suppression instruction signal is detected,
In each of the CPUs (0) to (n),
Reads out the new TOD value that has been set, and
The TOD clock is set, and the completion of the setting is recorded in the main storage device.
CPU with synchronization authority set in a predetermined area of
Notify (0) .

The CPU (0) having the synchronization right
Looking at a predetermined area of the storage device, all CPUs (0) to (n)
Confirms that has set a new TOD value,
Sends an event start instruction signal. Start this TOD count
Upon detecting the instruction signal, each TOD clock immediately counts.
To start .

Therefore, according to the present invention, a specific CPU
Occurs due to TOD clock count operation at (0)
Not a synchronization control based on a one-second carry signal
Therefore, there is no malfunction due to interference between CPUs, and
Since only one synchronization process is required, accurate synchronization
The effect that can be realized in mousse is obtained .

In particular, the suppression and start of the TOD clock count
Signal (TODCS-W) that connects a and b signals
A circuit for dot-oring by a circuit and transmitting to each CPU
By doing so, with less hardware, each CPU (0)
(N) can be controlled .

The timing of these signals is determined by each CP.
Count timing of TOD clock at U (0) to (n) (TOD
CE), so-called hazards
Problem can be avoided, and each CPU (0) to (n)
The start of TOD clock counting can be stabilized
You .

[0033]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 1 (a) shows an example of the entire configuration, and FIG.
FIG. 2 is a time chart of the TOD synchronization processing of the present invention, and FIGS. 3 and 4 are the timing charts of the DCS synchronizing unit and the generation circuit of the TOD clock count enable signal. FIG. 5 is a flowchart showing the processing, and FIG.
FIG. 9 is a view showing another embodiment of the present invention.

In the present invention, in a multiprocessor system in which a plurality of central processing units 1 each having a TOD clock 10 share a main storage unit 2, the instruction execution operation in each central processing unit 1 is stopped. Interrupt means and the TOD clock 1 provided in each central processing unit 1
By providing means a and b for inhibiting and starting the count operation of 0, the specific central processing unit 1 interrupts each central processing unit 1 by the above-mentioned interrupting means, and each central processing unit 1
After the instruction execution operation is stopped, the count suppression instructing means a of the TOD clock 10 instructs the suppression of the count of the TOD clock 10 provided in each central processing unit 1. When the count suppression instruction is recognized, the new central processing unit 1 reads the new TOD value and sets it in its own TOD clock 10, and the specific central processing unit 1 recognizes the completion of the setting of the new TOD value in each central processing unit 1. At this time, by instructing the start of counting by the count start means b of the TOD clock 10, each central processing unit 1 causes the new TO
Means for controlling to start counting from the D value is a means necessary for carrying out the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

The TOD synchronization control method of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, and 5. FIG.
Shows concrete means for synchronizing the TOD clock 10 in each CPU 1.

Referring to FIGS. 1A and 1B, TODCS 11 (TO
DCS-W) is a register in each of the CPUs (0) to (n) 1 and can be set for each of the CPUs (0) to (n) 1. EN
1M is the count timing of the TOD clock 10,
For example, 1τ is turned on at the fall of TODCK, which is a clock having a period of 1 μsec. << Refer to the operation time chart of FIG. 2 >> EN1MH is the TOD clock 1 in each CPU (0) to (n) 1.
0, and in this embodiment, the above TO
Since DCK has a duty ratio of 50, EN1M is turned on by 1 [tau] at a timing delayed by 0.5 [mu] sec as shown in FIG.

As is apparent from the specific circuit of FIG. 1B, the above TODCS-W is synchronized with the above EN1MH by the AND circuit 120 in the TODCE synchronization circuit 12 to constitute a holding circuit. As shown in FIG. 1 (a), the DOT is held by the D-type flip-flop (D) 121 and inverted by the next negation circuit 14, as shown in FIG. −
It is output as an OR signal. Then, each CPU (0)
~ (N) 1 captures the DOT-OR signal, and
Input to the clock count enable generation circuit (TODCE generation unit) 13.

In the TOD clock count enable generation circuit (TODCE generation unit) 13, the DOT-OR signal is inverted to the original polarity by the NOT circuit 130, and then, for example, two D-type flip-flops are used for waveform generation. (D) 131,132
Is inverted and input to the count enable suppression gate circuit 133, and the TODCS-R
During the period when SW is "1", the output of the count enable signal (TODCE) for counting the TOD clock 10 of each of the CPUs (0) to (n) 1 is suppressed.

Here, the output of the above TODCS 11 (TODCS
-W) is output to the DOT-OR, so any one C
When PU (0), (1), to 1 are turned on, the DOT-OR signal becomes “0”. Further, in order to set the DOT-OR signal to “1”, the TODCS-W of all CPUs (0) to (n) 1
Must be set to “0”. It is TOD clock 10
Is updated, there is only one update CPU 1 and the other CPUs 1 follow this method, which constitutes one of the features of the present invention.

When TODCS-R is "1", TODCS-R
The count of the D clock 10 is suppressed. When the count is "0", the count of the TOD clock 10 is performed. That is, the TODCS-W signal,
That is, as is clear from the time chart of FIG. 2, the TODCS-R signal is synchronized with the EN1MH, so that the count timing (EN1M
(The same timing as described above). Thus, as in the prior art, synchronization omission due to a slight difference between the count timing of the TOD clock 10 and the count suppression and the start timings a and b of the TOD clock 10, that is, so-called hazard operation in the TOD clock 10 Etc. can be prevented.

FIG. 3 shows an operation flow of each CPU when the TOD clock 10 is set. In this embodiment, each CPU
(0) to (n) 1 show the operation flow of each CPU when the TOD is set during the software operation (that is, the instruction is being executed).

First, the CP to which the TOD clock 10 is to be set
U1 obtains the TOD clock setting right by, for example, a test and set (T & S) instruction. More specifically, the CPU 1 that wants to set the TOD clock 10
Executes the (T & S) instruction and stores it in main memory 2 {see Fig. 1 (a)}.
Referring to the acquisition area of the TOD clock set right above,
Check if it is “0”, and if it is “0”, which C
PU 1 also recognized that he did not have the TOD clock set right,
By setting the area to “1”, the TOD clock set right is obtained. In the following, the other CPUs 1 already see “TOD clock set right acquired area” The exclusive control is performed such that the user cannot set "1" in this area any longer and cannot acquire the TOD clock set right. << Refer to the processing step 200 in FIG. 3. >>
Sets the new TOD value at a specific address in main memory 2,
A predetermined interrupt is issued to each of the other CPUs 1 to notify that the TOD clock is set (specifically, a request to stop the software operation). {See Processing Steps 201 and 202 in FIG. 3} When the software operation stops, each CPU 1 sets the stop to a specific address in main memory 2 and prepares for the TOD clock set. << Refer to processing steps 203 and 220 in FIG. 3. >> CPU 1, which has acquired the TOD clock setting right, confirms that all CPUs 1 have stopped the software operation by referring to the predetermined area in main memory 2 described above. By setting "1" in the TODCS 11, a TOD clock count suppression instruction a is issued. It is synchronized with EN1MH and DOT-O
The TODCS-R in each CPU 1 becomes “1” by the R signal. {Refer to processing steps 204, 205, and 221 in FIG. 3} Thereby, the count of the TOD clock 10 of each CPU 1 stops. After confirming that the TODCS-R has become "1", each CPU 1 reads the new TOD value, sets it in the TOD clock 10, and indicates in the main memory that the new TOD value has been set. Set the address. << Refer to the processing steps 206, 207, 208, 221, 222, and 223 in FIG.
Confirms that the new TOD value has been set by referring to the specific address in the main memory 2, sets “0” in TODCS-W, and sets the count start instruction b of the TOD clock to “on ( = 0) ”. It is synchronized with EN1MH and the DOT-OR signal causes each CPU 1
The data is input to the generation unit 13 and the counting of the TOD clock 10 of each CPU 1 is started.処理 Processing steps 209 and 21 in FIG.
0,224} In the above embodiment, the count suppression of the TOD clock from each of the CPUs (0) to (n) 1 and the start signal (TODCS-W) a,
b has been described as an example of dot-oring as shown in FIG. 1 (a), but as shown in FIG.
U (0) to (n) The count suppression of the TOD clock from 1 and the start signals (TODCS-W) a and b are sent to the respective CPUs (0) to
(n) It goes without saying that the logical sum of 1 may be taken in. In this case, FIG.
As shown in (1), there is no need to invert the polarity of the count suppression and start signals (TODCS-W) a and b of the TOD clock.

As described above, according to the present invention, in the multiprocessor system, in order to synchronize the TOD clock between the CPUs, the interrupt means for instructing each CPU to stop the instruction execution operation, Means a and b for suppressing and starting the count of the TOD clock are provided. The specific CPU obtains the right to acquire the TOD set, interrupts each CPU by the interrupt means, and stops the software operation of each CPU. Thereafter, the count of the TOD clock is suppressed by the TOD clock count suppression means a of each CPU. When the CPU recognizes the count suppression instruction, the CPU reads the new TOD value and sets it in its own TOD clock. When the specific CPU recognizes that the setting of the new TOD value in each CPU is completed, the count start means b of the TOD clock instructs the start of counting. In Rukoto, each C
It is characterized in that the PU starts counting from the new TOD value.

[0044]

As described above in detail, according to the TOD synchronization control method in the multiprocessor system of the present invention, 1 which occurs due to the counting operation of the TOD clock in the specific CPU (0). Since the synchronization control is not based on the carry signal of the second, there is no malfunction due to the interference between CPUs, and only one synchronization process is required.
An effect that an accurate synchronization process can be smoothly realized is obtained.

In particular, the TOD count suppression and start instruction (T
ODCS-W) Dot OR the signals of a and b, and
, The synchronization processing in each of the CPUs (0) to (n) can be controlled with a small amount of hardware.

The TOD count suppression and start instruction (TOD count
CS-W) The timing of the signals of a and b is
(N) can avoid the so-called hazard problem, and can stably start counting on the TOD clock in each of the CPUs (0) to (n). You can get started.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 is a time chart of the TOD synchronization processing of the present invention.

FIG. 3 is a flowchart showing the synchronization processing of the present invention (part 1).

FIG. 4 is a flowchart showing a synchronization process according to the present invention (part 2);

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 illustrates a multiprocessor system.

FIG. 7 illustrates a conventional TOD synchronization setting process (part 1).

FIG. 8 is a diagram showing a conventional TOD synchronization setting process (part 2);

[Explanation of symbols]

1 Central processing unit ｛CPU, CPU (0) to (n)｝ 10 TOD clock 11 TOD count suppression section (TODCS) 12 TOD count enable synchronization section (TODCE synchronization) 13 TOD count enable generation section (TODCE generation section) 200 to 210,220 to 224,230 to 233 Processing steps TDOCK TOD clock TDOCS-W TOD count suppression, start signal TODCE TOD count enable signal DOT-OR dot or interrupt means a, b TOD clock count operation suppression, start instruction means TODCS-R

Continuing from the front page (72) Inventor Koichi Odawara 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Takumi Nonaka 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Invention Person Eiji Kanaya 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A 1-211159 (JP, A) JP-A 61-13364 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 15/16-15/177

Claims (4)

(57) [Claims] 1. A plurality of centers each having a TOD clock.
A multiprocessor system having a processing unit , wherein one of the central processing units is authorized to perform TOD synchronization.
Synchronization authority acquiring means, and counting operation of the TOD clock provided in each central processing unit
Signal to instruct the start of the count operation.
A TOD count control signal means for transmitting a signal indicating the signal and a central processing unit having acquired the synchronization authority are provided in the main storage device.
Set a new TOD value in a certain area and assign it to another central processing unit.
And a central processing unit that receives an interrupt for TOD synchronization executes instruction execution.
Stops the row operation and sets the stopped state to a predetermined area in the main storage device.
The display setting means and the central processing unit having acquired the synchronization right
That the storage is in a stopped state is determined by a predetermined area of the main storage device.
Detected and at TOD via TOD count control signal means
TO that sends out a signal to instruct the counter to stop counting
D clock count suppression means , detecting a signal instructing suppression of the TOD clock count operation
The central processing unit reads the new TOD value and
Set the clock to D and display the setting completion in a predetermined area
The TOD setting means and the central processing unit having acquired the synchronization authority make all TOD values
Detects completion of setting, and outputs TOD count control signal
Indicates the start of the count operation of the TOD clock via the means
And a TOD count start means for transmitting a
And a multiprocessor system . 2. The multiprocessor system according to claim 1, wherein a signal instructing suppression of the count operation of the TOD clock is received.
The timing to take and the start of the count operation of the TOD clock
The timing of receiving the instructing signal means that each TOD clock
There is a timing that deviates from the count timing of
A multiprocessor system characterized by: 3. The multiprocessor system according to claim 1, wherein the TOD count control signal means receives a signal from each central processing unit.
It is characterized by a circuit configuration in which signal lines are dot-ORed.
Multiprocessor system . 4. A plurality of centers each having a TOD clock.
T in a multiprocessor system having a processing unit
An OD synchronization control method, wherein a specific central processing unit acquires an authority to perform TOD synchronization.
And the central processing unit that has acquired the synchronization authority is located in the main storage device.
Set a new TOD value in a certain area and assign it to another central processing unit.
And the central processing unit having received the TOD synchronization interrupt executes the instruction execution.
Stops the row operation and sets the stopped state to a predetermined area in the main storage device.
The display setting stage and the central processing unit having acquired the synchronization authority are connected to another central processing unit.
That the storage is in a stopped state is determined by a predetermined area of the main storage device.
Detect and detect the clock of the TOD clock provided in each central processing unit.
Signal to suppress counting operation and counting operation
TOD count control signal for transmitting a signal indicating start
Instructs the TOD clock to stop counting via line
A TOD clock count suppression stage that sends out a signal, and a signal that instructs suppression of the TOD clock count operation is detected.
The central processing unit reads the new TOD value and
Set the clock to D and display the setting completion in a predetermined area
The TOD setting phase, and the central processing unit that has acquired the synchronization authority determines all TOD values.
Detects completion of setting, and outputs TOD count control signal
Instructs the start of TOD clock count operation via line
A signal is sent and each TOD starts counting.
And a multi-start stage.
A TOD synchronization control method in a Sessa system .