JPS63204424A - Timer device - Google Patents

Abstract

PURPOSE:To obtain plural output signals each having delay time small in difference regardless of the processing speed of a CPU, by supplying the common input signals and clock signals to plural timer circuits and setting different comparison data. CONSTITUTION:The external triggerable timers ETT 1 and ETT 2 which produce input signals start counting actions to produce signals ETE 1 and ETE 2 for each prescribed count value. Then new comparison data are set at the comparison registers incorporated into the ETT 1 and ETT 2 by the signal ETE 1 of a prescribed ordinal number. Thus the output signals having the prescribed time delays from input signals by the signal ETE 1 of the next ordinal number via output registers 8 and 9 and D type FF 10 and 11 respectively. As a result, plural output signals having slightly different delay times are obtained via a CPU having a low processing time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timer device using a timer circuit that automatically starts when an external input signal is used as a trigger.

[Summary of the invention]

In this invention, an input signal and a clock signal are supplied,
In a timer device using a timer circuit that generates an output signal after a predetermined time determined by comparison data and the number of clock signals from a timing determined by a human input signal, a timer circuit having a first time delay with respect to an input signal is used. When obtaining one output signal and a second output signal having a second time delay with respect to the input signal, the same comparison data is set in the first and second timer circuits, and depending on the input signal, The first and second timer circuits are started at the same time, and after a predetermined time obtained from one of the timer circuits, different comparison data is set in the first and second timer circuits. This prevents the increase in the processing time, thereby shortening the processing time.

[Conventional technology]

In a microcomputer, as shown in Figure 5,
In order to generate an output signal with a precise time delay T (e.g. 900 IIs) from the rising edge of the input signal,
ETT (External TriggerbleT
A timer device using a timer circuit called ``timer'' is known.

FIG. 6 shows an example of a conventional timer device. In FIG. 6, reference numeral 21 surrounded by a broken line is a timer circuit (ETT). The ETT 21 is supplied with comparison data from, for example, an internal bus 22 of the microcomputer. This comparison data is taken into the data register 23 inside the ETT 21 and transferred from the data register 23 to the comparison register 24. The comparison data from the comparison register 24 is supplied to the coincidence detection circuit 25! - The match detection circuit 25 is supplied with the count data of the counter 26, and when both the comparison data and the count data match, a detection signal ETE is generated from the one-defeat detection circuit 25.

The counter 26 is supplied with a clock signal via a logic circuit 29. The logic circuit 29 is supplied with an input signal from the input terminal 27 and a clock signal from the input terminal 28, and the logic circuit 29 converts the clock signal from the rising edge of the input signal to the counter 2.
6, and the counting operation of the counter 26 starts. The clock signal has a constant period, for example, a period of 1 μs. Both comparative data and counting data are
This is 8-bit data.

The signal ETE from ETT21 is sent to D flip-flop 3.
1 clock input. Data from the output register 30 is supplied as a data input to the D flip-flop 31 . The output register 30 stores data from the internal bus 22, and the data is transferred from the output register 30 to the D flip-flop 3E by the signal ETH, and an output signal is obtained at the output terminal 33 via the buffer 32. This D flip-flop 31. The buffer 32 is
Configure output ports.

Furthermore, the signal ETE from the -number output circuit 25 is output to the output terminal 3.
4 and is also supplied to the comparison register 24 and counter 26 as a load signal. The comparison register 24 and the counter 26 are provided with the following signals by the signal ETE.
Predetermined initial values are loaded. Further, a signal ETE from the ETT 21 is supplied to the CPU (not shown). C.P.
tJ runs an interrupt program when signals F and TE occur. The CPU writes data to the data register 23 and switches modes using the internal bus 22.
control through.

As shown in Fig. 5, T (900 μs
The operation when obtaining an output signal with a delay of ) will be described with reference to FIGS. 7 and 8.

The flowchart in FIG. 7 shows the steps of the preparation process before the input is generated and the interrupt process performed after the signal ETE is generated. In the preparation process, 250 μs is stored as comparison data in the data register 23 (FA
) (in hexadecimal) is sent (step ■). Next, the contents of the data register 23 are transferred to the comparison register 24 (step 2).

When the input signal is generated, the counter 26 starts counting, and the count data of the counter 26 is supplied to the coincidence detection circuit 25. When this count data reaches [FA], -
A signal ETE is generated from several output circuits 25. Signal ETE
runs the interrupt program. The interrupt program checks whether the number of interrupts Ni is 2 (step ■). (Ni=2), the comparison data [96
] is set (step ■).

In step ■, when (Ni≠2), (Ni=3
) can be checked (step ■).

If the number of interrupts Ni is the third, output register 3
A low level is set to 0 (step ■).

The above operation will be explained with reference to FIG. 8. FIG. 8A shows an input signal, and the counter 26 of the ETT 21 starts counting from the rising edge of this input signal. High level data is set in the output register 30, as shown in FIG. 8F. 8-bit data [FA] corresponding to 250 .mu.s is stored in advance in the data register 23 and the comparison register 24, as shown in FIGS. 8C and 8, respectively. Therefore, every time the count data of the counter 26 reaches (FA), the signal E shown in FIG.
TE occurs.

Due to the second signal ETE, the data register 23 has the following information:
As shown in Figure 8C, comparative data [96] (150 μ
s> is set. Therefore, new comparison data [96] is set in the comparison register 24 by the third signal ETH. This third signal ETE sets the output register 30 to a low level as shown in FIG. 8E.

Since the data of this output register 30 is taken into the D flip-flop 31 by the fourth signal ETH, the output signal goes to low level 150 pS after the third signal ETE is generated, as shown in the 8th Na. Go down. Therefore, from the edge of the input signal (T=250μs×3
An output signal with a time delay of +150 μ5 = 900 μs) can be obtained.

The above-mentioned timer device obtains one output signal having a time delay T with respect to the input signal, as shown in FIG. As a more complicated case, as shown in FIG. 4, a time delay Tl (for example, 900
j! Regarding the case of obtaining both a first output signal (FIG. 4B) with a) and a second output signal (FIG. 4C) with a second time delay T2 (for example, 910 μs) with respect to the input signal. explain.

FIG. 9 shows an example of a possible configuration for obtaining the first and second output signals having the relationship shown in FIG. 4. For the configuration shown in FIG. 6, output register 35. D flip-flop36. A buffer 37 is added, from which an output terminal 38 for a second output signal is connected.

[Problem that the invention seeks to solve]

In the configuration of FIG. 9 as well, by the same operation as the above-described timer device, the control regarding the second output signal is delayed by one signal ETE with respect to the control regarding the first output signal having the time delay T1. By performing the control, two output signals can be obtained. However, as in the example shown in FIG. 4, (TI=900μ5) (T2=910μs)
When the difference between the time delays T1 and T2 is small, as shown in FIG. 2, it is necessary to rewrite the output register 35 during this time difference (10 μa). This requires the processing speed of the CPU to change quite quickly, and as in the example above,
When there is only a time difference of μ3, it is impossible to rewrite the output register 35.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a timer device that can obtain two or more output signals each having a delay time with a fairly small time difference with respect to an input signal.

[Means for solving problems]

In this invention, an input signal and a clock signal are supplied,
In a timer device using a timer circuit (ETT) that generates an output signal after a predetermined time determined by comparison data and the number of clock signals from a timing determined by an input signal, a first timer circuit ETTI and a second timer circuit E are provided.
TT2 is provided, and first and second timer circuits ETTl
The same comparison data is set in ETT and ETT2, and the first and second timer circuits ETTI and ETT2 are started simultaneously by a human input signal, and the predetermined data obtained from one of the first and second timer circuits ETTI and ETT2 is set. After a period of time, different comparison data are set in the first and second timer circuits ETTI and ETT2, and a first output signal having a first time delay T1 with respect to the input signal is obtained, and the input A second output signal is obtained with a second time delay T2 relative to the signal.

[Effect]

Two timer circuits 1ETT1 and ETT2 are provided, to which the input signal J and the clock signal are both supplied, and the timer operations are started at the same time.

In addition, since the same comparison data is initially set in ETT1 and ETT2, the signal ETT1 and ETT2 are set at the same timing.
E1 and ETE2 occur. If the time delay T1 of the first output signal with respect to the human input signal and the time delay T2 of the second output signal with respect to the input signal are (T2>Tl), the time determined by the same comparison data set initially is repeated multiple times. , different comparison data are set for ETTI and ETT2 after repeated predetermined times. This comparison data ultimately defines the time delays T1 and T2.

In this invention, unlike rewriting the output buffer to obtain the second output signal after the time delay Tl, sufficient time is secured to rewrite the output buffer, and the CP
The processing speed of U does not need to be very high. In addition, since the interrupt program is run by the signal ETE from one ETT (timer circuit), unlike running the interrupt program by the signals from both ETTs, it is possible to prevent the number of interrupt factors from increasing, and during the entire processing time. The interrupt processing time occupied can be reduced. Therefore, the processing speed of C
In the case of PU, it is possible to avoid the inconvenience of not being able to perform other processes that require time precision.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG. 4, the input signal (FIG. 4A) is delayed by a time T1 (for example, 900 .
1/3) (Fig. 4B) and a second output signal (Fig. 4C) with a second time delay T2 (e.g. 910 μs) relative to the input signal. This invention is applicable to all cases.

As shown in FIG. 1, the first timer circuit (ETT:
External Trigger Timer
)l and a second ETT2 are provided. E.T.
Comparison data is set in Tl and ETT2 via the internal bus 3. Further, an input signal from the input terminal 4 and a clock signal with a constant period (1 μs) from the input terminal 5 are supplied to the ETTI and the ETT2. ETTI and ET
In T2, the comparison data is set in the comparison register from the internal bus 3 via the data register, and the clock signal is counted by the counter from the timing synchronized with the rising edge of the human input signal, and the count value of the counter and the comparison register are set. The comparison data thus obtained are compared by a coincidence detection circuit, and when the two match, signals ETE1 and ET are
E2 is generated respectively.

The signal ETE 1 from ETTl is used as the clock input of the D flip-flop 10. D flip-flop lO
The data in the output register 8 is supplied as the data input. The output register 8 stores data from the internal bus 3, and the data is transferred from the output register 8 to the D flip-flop 10 by the signal ETEI, and the first output signal is sent to the output terminal 14 via the buffer 12. is obtained. This D flip-flop10. Buffer 12 constitutes an output port.

Historically, the signal ETE1 from ETTI is taken out to the output terminal 6 and is supplied as a load signal to the data register and counter of ETT1. The comparison register and counter are loaded with predetermined initial values by signal ETEI.

Further, a signal ETE1 from ETT1 is supplied to the CPU (not shown). The CPU runs the interrupt program when the signal ETE1 occurs.

cpv controls writing of data to the data registers of ETT1 and ETT2 and mode switching through the internal bus 3.

ETT2 has the same configuration as ETTl, and E'"T2
A signal ETE2 from the D flip-flop 11 is taken out to the output terminal 7 and is also used as a clock input to the D flip-flop 11. D
The data from the output register 9 is supplied to the flip-flop 11, and the output signal of the D flip-flop 11 is taken out as a second output signal to the output terminal 15 via the buffer 13.
Interrupts caused only by I are allowed, and interrupts caused by signal ETE2 are not allowed.

As shown in Figure 4, for the input signal (Figure 4A)
Regarding the operation when obtaining the first output signal (Figure 4B) with a delay of I (900 μs) and the second output signal (Figure 4C) with a delay of T2 (910 μs) with respect to the input signal , will be explained with reference to FIGS. 2 and 3.

The flowchart of FIG. 2 shows steps 11V1 of the preparation process before the input is generated and the interrupt process performed after the signal ETE1 is generated. In the preparation process, E
250μs as comparison data in the data register of TTl
[FA] (in hexadecimal) corresponding to is set (step ■). Similarly, 25 is added to the data register of ETT2.
CFA3 (in hexadecimal notation) corresponding to 0 μs is set (step ■). Next, the contents of the data register are transferred to the comparison register of the ETTI (step ■).

Similarly, the contents of the data register are transferred to the comparison register of ETT2 (step 2).

When an input signal is generated, the counters of ETT1 and ETT2 start counting operation, and the count data of the counters becomes (F
When A) is reached, signals ETE1 and ETE2 are generated. Only the signal ETEI runs the interrupt program. The interrupt program checks whether the number of interrupts Nf is 2 (step ■). In the case of (Ni=2), comparison data [96] corresponding to 150 μs is set in the data register of ETTl (step ■). Next, 16Q ps is sent to the data register of ETT2.
and the corresponding data CAO] are set (step ■
).

In step ■, when (Ni≠2), (Ni=3
) can be checked (step ■).

When the number of interrupts Ni is the third, output register 8
A low level is sent to (step ■). Next, a low level is set for the output register 9 (step [phase]).

The above operation will be explained with reference to the time chart of FIG. 3. FIG. 3A shows a human input signal, and the counters of ETT1 and ETT2 start counting operations from the rising edge of this input signal. High level data is set in the output register 8, as shown in FIG. 3H, and high level data is set in the output register 9, as shown in FIG. 3J. The data registers and comparison registers of ETTl and ETT2 include Figure 3, Figure 3E,
As shown in Figure 3F and Figure 3G, respectively, the front 250
I! 8 focus data [FA] corresponding to s is set. Therefore, from ETT1 and ETT2, each time the count data of each counter becomes (FA),
and signals ETEI and ETE2 shown in FIG. 3C, respectively, are generated.

By the second signal E T E' 1, the comparison data (
96) (150 μs) is set. Therefore, new comparison data [96] is sent to the comparison register of ETTl by the third signal ETE1. This third signal ETE1 sets the output register 8 to a low level as shown in FIG. 3H.

On the other hand, the comparison data (AO) (1601!s) is set in the data register of ETT 2 by the second signal ETE 1, as shown in FIG. 3H.

Therefore, new comparison data (AO) is sent to the comparison register of ETT2 by the third signal ETEI. This third signal ETE1 sets the output register 9 to a low level as shown in FIG. 3J.

Since the data in the output register 8 is taken into the D flip-flop 10 by the fourth signal E T El, as shown in the third [ff1r], 150 μs after the third signal E is generated, the first The output signal falls to low level. Therefore, from the edge of the input signal (T=2
A first output signal with a time delay of 50 μs×3+150 μ5=900 μs) is obtained.

Similarly, the data in the output register 9 is the fourth signal ETE.
1 is taken into the D flip-flop 11, so that the second output signal falls to a low level 160 pS after the third signal ETE1 is generated, as shown in FIG. 3K. Therefore, from the edge of the input signal (T=
A second output signal is obtained with a time delay of 250μaX3+150μ5=910//a).

It should be noted that the present invention can be applied similarly to this embodiment even when three or more output signals having mutually different time delays are obtained with respect to an input signal.

〔Effect of the invention〕

In this invention, a plurality of timer circuits operate in synchronization with a common input signal and a common clock signal, and an interrupt program is run using only the signal ETE1 from one timer circuit. .

Therefore, according to the invention, a plurality of output signals having slightly different delay times can be obtained by a slow CPU. Furthermore, according to the present invention, since the number of interrupt factors does not increase, it is possible to prevent the processing time from increasing.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a flowchart showing the operation of the embodiment, Fig. 3 is a time chart showing the operation of the embodiment, and Fig. 4 is the input of the embodiment. FIG. 5 is a waveform diagram showing the relationship between signals and output signals; FIG. 5 is a waveform diagram used to explain the timer circuit that can be used in the present invention; FIG.
The figure is a block diagram of a timer circuit that can be used in this invention, and FIGS. 7 and 8 are flowcharts and time charts used to explain the timer circuit that can be used in this invention. Explanation of main symbols in the drawings 1. 2: ETT, 3: Internal bus, 4: Input signal input terminal, 5: Clock signal input terminal, 8°9: Output register, 10. l'l: D flip-flop, tt, ts:
Output terminal. Agent Patent Attorney Tadashi Sugiura 1st Group Figure 3 Flow 10 Yards Figure 2 Figure 4 (2900JJS) Figure 5 Time, +, -) Figure 8 Procedure Correction Amount May 6, 1985 1. Indication of the case Patent Application No. 37382 of 1988 2. Name of the invention Timer device 3. Person making the amendment Relationship to the case Patent applicant address 6-7-35, Kitashinyo, Tokyo Parts Co., Ltd. Name ( 2
18) Sony Corporation Representative Director Norio Oga 4, Agent 170 Address 1-48-10 Higashiikebukuro, Toshima-ku, Tokyo” April 28, 1986 6, Column for a brief explanation of the drawing subject to the amendment ') (', 5.-r 7. In the description of contents of the amendment, page 20, line 11, the following is added after "Time chart". ", Figure 9 is for reference in the explanation of this invention. Block diagram of another example of the timer device used

Claims (1)

[Claims] A timer device using a timer circuit that is supplied with an input signal and a clock signal and generates an output signal after a predetermined time determined by comparison data and the number of the clock signals from the timing defined by the input signal. , a first timer circuit and a second timer circuit are provided, the same comparison data is set in the first and second timer circuits, respectively, and the first and second timer circuits are started simultaneously by an input signal. , after a predetermined time obtained from one of the first and second timer circuits, the first and second timer circuits
By setting different comparison data to the timer circuits, a first output signal having a first time delay with respect to the input signal is obtained, and a second time delay with respect to the input signal is obtained. A timer device characterized in that a second output signal with a delay is obtained.