JPS63211449A - Device number setting system - Google Patents

Abstract

PURPOSE:To prevent an erroneous setting by providing an automatic device number setting circuit on an input/output controller, and also, cascading each input/output controller in accordance with a prescribed sequence. CONSTITUTION:An automatic device number setting circuit 507 identifies whether a signal line 6 from a pre-positioned input/output controller 5 is connected or not. When the signal line 6 from the pre-positioned input/output controller 5 is connected, the automatic device number setting circuit 507 counts a number setting pulse transferred from the pre-positioned input/output controller 5 through the signal line 6, sets a device number, based on its counting value, and also, sends out the number setting pulse which is subtracted one pulse from the number setting pulse transferred from the pre-positioned input/output controller 5, to the number setting signal line 6 which reaches the post-position. In such a way, the device number of each input/output controller 5 connected to an input/output bus 4 is set automatically, and an erroneous setting caused by an operation error, etc. is prevented.

Description

[Detailed Description of the Invention] [Summary] When a plurality of input/output control devices are activated from a channel control device via an input/output bus, a predetermined number of number setting pulses are sent from the input/output control device with the most recent value to the next one. The next input/output control device reduces the number of number setting pulses transmitted from the previous human output control device by one and transmits the result to the next input/output control device. , each input/output control device automatically sets a device number corresponding to the number of number setting pulses sent to the next input/output control device, thereby simplifying the device number setting work and preventing erroneous settings.

[Industrial application field]

The present invention provides device number setting that simplifies the task of assigning a device number to each input/output control device in an information processing system in which a plurality of input/output control devices connected to an input/output bus are controlled by a channel control I device. Regarding the method.

In an information processing system, in order for a channel control device to specify an input/output control device to be controlled from among a plurality of input/output control devices, it is necessary to assign a unique device number to each input/output control device.

This type of device number is not only assigned to input/output control devices installed at the initial stage of an information processing system, but also new numbers are assigned to input/output control devices, including existing input/output control devices, each time an input/output control device is added. Grant is required.

Therefore, it is desirable that this type of device number assignment work be simplified as much as possible, taking into account the fact that the number of input/output control devices connected to information processing systems is on the rise.

[Conventional technology]

FIG. 5 is a diagram showing an example of an information processing system to which the present invention is applied, FIG. 6 is a diagram showing an example of an input/output control device address, and FIG. 7 is a diagram showing an example of a conventional device number register. FIG.

In FIG. 5, a plurality of input/output control devices (IOC) 5
(Hereinafter, specific input/output control devices will be referred to as 5-1, 5-2, etc., and the same will apply hereinafter) are connected to the input/output bus 4.

Each input/output control device 5 is assigned a unique input/output control device address a.

Each input/output control device address a, as shown in FIG. Attribute information m (8 bits) indicating the same attribute information m, device number n (4 bits) for mutually identifying input/output control devices 5 having the same attribute information m, and each input/output control device 5
It consists of an internal register number 0 (4 pinto) that identifies various registers provided within the register.

In each input/output control device 5, an attribute register (ZR
) 501 and device number register (NR) 502 are set with attribute information m and device number n, respectively.

When the channel control device (CHC) 3 controls an arbitrary input/output control device 5, the address a assigned to the input/output control device 5 to be controlled is sent to the address bus 41 constituting the input/output bus 4. Send.

The attribute information m, device number n, and internal register number O included in the sent input/output control device address a are sent to the coincidence detection circuit (MC) 503, 504 in each input/output control device 5 via the address bus 41. and decoder (OCR)
505 respectively.

Each coincidence detection circuit 503 compares the attribute information m arriving from the address bus 41 with the attribute information m set in the attribute register 501, and when it detects that the two match, it sets the output signal to logic "1". Set to .

Furthermore, each coincidence detection circuit 504 compares the device number n arriving from the address bus 41 with the device number n set in the device number register 502, and when it detects that the two match, it outputs a logic “ Set to 1”.

Furthermore, decoder 505 specifies the internal register corresponding to internal register number 0 arriving from address bus 41.

In the input/output control device 5 in which the output signals from the coincidence detection circuits 503 and 504 are both set to logic "1",
When the activation signal transmitted from the channel control device 3 via the control line 43 is set to logic "1", the activation signal generator 506 outputs an input/output control device internal activation signal of logic "1", Control of the channel control device 3 is enabled to accept control.

- In the input/output control device 5 where the number output circuit 503 or 504 detects a mismatch and the output signal is set to logic "0", the activation signal generator 506 activates the input/output control device with logic "0". In order to output the signal, control of the channel control device 3 is set to a state in which reception is disabled.

The device number register 502 has a configuration as shown in FIG. potential), or logic “1” (+
potential).

Therefore, when setting or changing the input/output control device address a of each input/output control device 5, each input/output [problem to be solved by the invention] As is clear from the above explanation, the conventional device number setting method is used. In order to set the device number n to each input/output control device 5, it is necessary to operate each switch 511 to 514 provided in the device number register 502, which increases the number of input/output control devices 5. Accordingly, the number of man-hours required for setting the device number n increases, and there is also a risk that the device number n may be set incorrectly due to an operational error.

Measures to solve problem C] FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 3 is a channel control device, 4 is an input/output bus, and 5 is an input/output control device.

Reference numeral 6 denotes a signal line that cascades the input/output control bags N5 according to the present invention in a predetermined order.

507 is a device number automatic setting circuit provided in each input/output control bag W5 according to the present invention.

[Effect]

The device number automatic setting circuit 507 identifies whether or not the signal line 6 from the preceding input/output control device 5 is connected, and determines whether the signal line 6 from the preceding input/output control device 5 is not connected. In this case, a predetermined number of number setting pulses i,
It is sent to the signal line 6 leading to the downstream input/output control device 5, and the device number n corresponding to the sent number setting pulse i is set in the own device.

On the other hand, when the signal line (6) from the preceding input/output control device 5 is connected, the device number automatic setting circuit 507 receives the signal from the preceding input/output control device 5 via the signal 'fa6. The number setting pulse i is counted and the device number n is set based on the counted value, and the number setting pulse i is set after subtracting one pulse from the number setting pulse i transmitted from the preceding input/output control bag W5. It is sent to the number setting signal line 6 leading to the number.

Therefore, the device number of each input/output control device connected to the input/output bus is automatically set, eliminating the need for setting the device number, and also preventing the possibility of incorrect settings due to operational errors. Ru.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, FIG. 3 is a diagram showing a device number automatic setting circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing an information processing system according to an embodiment of the present invention. FIG. 4 is a diagram illustrating various signal waveforms, and FIG. 4 (fa) is a diagram related to the foremost input/output control device, and FIG. The same reference numerals indicate the same objects.

In FIG. 2, a plurality of input/output control devices (IOC) 5-1.5-2.5-3, . . . are connected to the input/output bus 4.
... are each equipped with a device number automatic setting circuit (NST).
) 507 is provided.

From the most advanced input/output control device 5-1 closest to the channel control device (CHC) 3, to the succeeding input/output control device 5-2
．． 5-3, . . . are connected to number setting signal lines 61 and 62.

In each input/output control device 5, number setting signal lines 61 and 62 connecting with the preceding input/output control device 5 are connected to terminals II and R1 of the device number automatic setting circuit 507, respectively.
The number setting signal lines 61 and 62 which are connected to the rear input/output control device 5 are 1. They are respectively connected to terminals IO and RO of device number automatic setting circuit 507.

Note that the number setting signal lines 61 and 62 from the preceding input/output control device 5 are not connected to the terminals II and RI of the device number automatic setting circuit 507-1 in the foremost input/output control device 5.

Note that the internal clock signal Ci in each device number automatic setting circuit 507 is constantly supplied from within each input/output control device 5.

In this state, the reset signal r transmitted from the channel control device 3 to each input/output control device 5 via the input/output bus 4 is at logic "1" (the reset signal rn is at logic "0").
), each device number automatic setting circuit 50
Both flip-flops 522 and 523 of No. 7 are in a set state, and flip-flops 529, 531,543 and counting circuit 538 are in a reset state.

In FIGS. 3 and 4 (al), in the device number automatic setting circuit 507-1 in the frontmost input/output control device 5-1, number setting signal lines 61 and 62 are connected to terminals II and R1. driver 526 and 52
Since ten potentials are supplied to the input terminals of 8 through resistors 525 and 527, an output signal of logic "1" is output, making gates 524 and 544 conductive.

As a result, a number setting reset signal ro of logic "1" is outputted to the number setting signal line 62 extending from the terminal RO to the rear input/output control device 5-S.

In order to automatically set the device number n to the human output control device 5, from the channel control device 3 to each input/output control device (IOC:) 5
When the reset signal r of logic "0" is transmitted to the device, the flip-flop 522 of each device number automatic setting circuit 507 is reset in synchronization with the device internal clock signal Ci, and sets the output signal q1 to logic "0". Then, the flip-flop 523 is reset in synchronization with the internal clock signal Ci inverted by the NOT circuit 521, and the output signal q2 is set to logic "0".

In the device number automatic setting circuit 507-1, the output signal g1 from the gate 524 is output from the time when the output signal q1 is set to logic "O" until the output signal q2 is set to logic "0". becomes logic “1”.

As the output signal g1 changes from logic "1" to logic "0", the flip-flop 529 is set and sets the output signal q3 to logic "1".

The output signal q3 of logic "1" turns on the gate 533 and is inputted to the counting circuit 538 via the gate 535 as an enable signal.

The internal clock signal C1 of the fruiting device is connected to the gate 533.5.
34 and the driver 537 from the terminal RO as a number setting pulse it onto the number setting signal line 61 that reaches the rear input/output control device 5-2.
38.

The counting circuit 538 counts the input number setting pulses if, outputs the counting results to the terminals QO to Q3 in binary format, and when the counted value reaches "F" (hexadecimal display), the logic "
A carry signal cr of 1" is output.

The flip-flop 543 receives a carry signal c of logic “1”.
When r is input, it is set in synchronization with the internal clock signal Cin of the inverter, and sets the output signal q5 to logic "0".

When the output signal q5 is set to logic "0", the flip-flop 529 is reset and the output signal q3 is set to logic "0".
”, the gate 533 is set to a cutoff state, and
The input of the enable signal to the counting circuit 538 is stopped.

As a result, the number setting pulse io sent from the terminal IO to the number setting signal line 61 is stopped at 15 pulses, and the count value of the counting circuit 538 is held at "F" (in hexadecimal notation).

In addition, the number setting reset signal ro output from the terminal RO
becomes logic “0”.

The device number automatic setting circuit 507-1 receives the count value "F" (
(in hexadecimal notation) is logically inverted by the NOT circuits 539 to 542, and 10° is outputted as the device number n of the foremost input/output control device 5-1.

Next, in FIG. 3 and FIG. 4(b), terminals II and R1 of the device number automatic setting circuit 507-2 in the input/output control device 5-2 are connected to terminals 10 and R1 of the device number automatic setting circuit 507-1. While the reset signal r transmitted from the channel control device 3 via the input/output bus 4 is set to logic "1" (reset signal rn is logic "0"), the device Number automatic setting circuit 5
The number setting pulse 10 output from 07-1 is logic “O”.
Since the number setting reset signal ro is set to logic "1", the driver 526 outputs a logic "0" output signal, making the gate 524 conductive, and the driver 528 outputs a logic "0" output signal. An output signal of "1" is output to turn on the gate 544, and a number setting reset signal ro of logic "1" is output to the number setting signal line 62 extending from the terminal RO to the rear input/output control device 5-3. .

A logic “0” is sent from the channel control device 3 to each input/output control device 5.
” When the reset signal r is transmitted, the input/output control device 5
-2 also in the device number automatic setting circuit 507-2,
The flip-flops 522 and 523 are sequentially reset and the output signals q1 and q2 are sequentially set to logic "0", but since the gate 524 is in the cutoff state, the output signal g1 is
is held at logic "O", and flip-flop 529 also holds the reset state.

Subsequently, when the first number setting pulse ii arrives at the terminal II from the device number automatic setting circuit 507-1 via the number setting signal +4iA61, the flip-flop 531 is set and the output signal q4 is set to logic "1". Set to .

The output signal q4 turns on the gate 536 and is inputted to the counting circuit 538 via the gate 535 as an enable signal.

The second to fourteenth number setting pulses ii of the fruiting device are:
Number setting pulse i from terminal RO via gate 536,534 and driver 537.

The signal is sent out onto the number setting signal line 61 leading to the rear input/output control device 5-3 as well as input into the counting circuit 538.

The counting circuit 538 counts the input second to fifteenth number setting pulses it, and displays the counting result "E" (in hexadecimal notation).
is output in binary format to terminals QO to Q3.

When the fifteenth number setting pulse if has finished arriving, the number setting reset signal ri arriving from the device number automatic setting circuit 507-1 becomes logic "0", the output signal of the driver 528 also becomes logic "0", and the gate 532 and 544 are in a cut-off state.

As a result, the flip-flop 531 is reset, setting the output signal q4 to logic "0", and the number setting reset signal being sent to the number setting signal line 62 from the terminal RO to the rear input/output control device 5-3. Signal ro is set to logic °O''.

When output signal q4 is set to logic “0”, gate 53
6 is cut off, and input of an enable signal to the counting circuit 538 is stopped. As a result, the counting circuit 538
The count value is held as “E” (hexadecimal notation).

The device number automatic setting circuit 507-2 receives the count value “E” output from the terminals QO to Q3 of the counting circuit 538.
“1” whose logical value is inverted by the NOT circuits 539 to 542
is output as the device number n of the human output control device 5-2.

Thereafter, in the same manner, number setting pulses ii of 13 pulses to O pulses and number setting reset signals ri are transmitted to the input/output control devices 5-3 to 5-15, respectively, and each device number ° automatic setting circuit 507- 3 to 507-15 set "2" to "15" as the device number n, respectively.

As is clear from the above description, according to this embodiment, when the reset signal r of logic "0" is transmitted from the channel control device 3 to each input/output control device 5, the devices in each input/output control device 5 The number automatic setting circuit 507 automatically sets each device number n in sequence.

Note that FIGS. 2 to 4 (BL are only one embodiment of the present invention; for example, the device number n is not limited to 0 to 15, and many other modifications may be considered. In either case, the effects of the present invention remain the same.

〔Effect of the invention〕

As described above, according to the present invention, the device number of each individual output control device connected to the input/output bus is automatically set, eliminating the need for device number setting work, and erroneous setting due to operational error etc. The fear of this is also prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the invention, FIG. 2 is a diagram showing an information processing system according to an embodiment of the invention, and FIG. 3 is a diagram illustrating an automatic device number setting circuit according to an embodiment of the invention. Fourth
The figure is a diagram illustrating various signal waveforms in Figure 3.
Figure (a) relates to the input/output control device at the forefront, and the fourth
Figure (bl is the 5th one related to the next input/output control device)
FIG. 6 is a diagram showing an example of an information processing system to which the present invention is applied, FIG. 6 is a diagram showing an example of an input/output control device address,
FIG. 7 is a diagram showing an example of a conventional device number register. In the figure, 1 is the central processing unit (CPU), 2 is the main memory (MM), and 3 is the channel control unit (CHC).
, 4 is an input/output bus, 5 is an input/output control device (IOC),
6. 61 and 62 are number setting signal lines, 41 is an address bus, 42 is a data bus, 43 is a control line, 501 is an attribute register (ZR), and 502 is a device number register (NR
), 503 and 504 are coincidence detection circuits (MC), 50
5 is a decoder (DCR), 506 is a start signal generator, 511 to 514 are switches, 507 is a device number automatic setting circuit (NST), 515 to 518, 525 and 527 are resistors, 521 and 539 to 542 are negative circuits , 522.523.529.531 and 543 are flip-flops, 524.530.5321.533
．． 534.535.536 and 544 are gates, 52
6.528 and 5 Kitani's principle flash broom 1 圀＄2 圀釧 ytake j りいい & ふくめ each 3rd figure rσ C! y′7 Depression・4th hearing

Claims (1)

[Claims] A plurality of input/output control devices (5) are connected to an input/output bus (4), and a device number (n ) in an information processing system that specifies and controls a signal line (6) that cascades each of the input/output control devices (5) in a predetermined order; Setting circuit (
The device number automatic setting circuit (507) identifies whether or not the signal line (6) from the preceding input/output control device (5) is connected, and ) is not connected, a predetermined number of number setting pulses (i) are
It is sent to the signal line (6) leading to the downstream input/output control device (5), and the device number (n) corresponding to the sent number setting pulse (i) is set as its own device number (n). If the signal line (6) is connected, the number setting pulse (i) transmitted from the preceding input/output control device (5) via the signal line (6) is The device number (n) is set based on the counted value, and a number setting pulse (i) is generated by subtracting one pulse from the number setting pulse (i) transmitted from the preceding input/output control device (5). ) is sent to the number setting signal line (6) leading to the downstream device.