JP2674858B2 - DMA controller with function capable of multiple operations - Google Patents

Description

The present invention relates to a DMA controller, and more particularly to a DMA controller having a function capable of performing multiple operations.

[Prior Art] Conventionally, this type of DMA controller has a plurality of unique DMA channels, one temporary address register that holds an address for performing DMA transfer, and one temporary word counter that holds the number of times DMA transfer is performed. It has registers and performs DMA service.

[Problems to be solved by the invention]

Since each DMA channel is shared in the above-mentioned conventional DMA controller, when one DMA channel is in service, other DMA channels cannot be in service until all the DMA operations of that channel are completed. For this reason, even if an I / O controller connected to another DMA channel issues a DMA service request to this DMA controller, it will wait until the service of the previous DMA channel ends. Therefore, an overrun error may occur. Then, in order to avoid this overrun error, there is a drawback in that the program must be controlled so that the DMAs of the respective channels do not compete with each other to cause an overrun error.

[Means for solving the problem]

A DMA controller with a function capable of performing multiple operations according to the present invention is a base address register that holds an initial address for performing independent DMA transfer and a value that is stored once in the base address register connected to a data bus. DMA
A current address register that holds the value changed by 1 for each transfer, a temporary address register that holds the value held by the current address register by connecting to the address bus, and a base word count register that holds the number of DMA transfers And once connected to the data bus DMA
A current word count register that holds a value that is decremented by 1 from the value that the base word count register holds for each transfer, and a temporary word count that holds the value held in the current word address register by connecting to the address bus Registers are provided for each of a plurality of DMA channels, and a DMA controller is programmed for the rotation priority and each DMA channel is set to a single transfer mode.

[Action]

According to the present invention, DMA transfer can be performed independently for each DMA channel.

〔Example〕

FIG. 3 is a block diagram showing an embodiment of a DMA controller with a function capable of performing multiple operations according to the present invention. In the figure, 1 is a data bus, 2 is a data bus buffer, 3 is a mode register, 4 is a status register, 5 is a command register, 6 is a mask register, 7 is a request register, 8 is a priority determination circuit, and 9 is Address bus buffer, 10 is a hold request signal line, 11 is an address bus, and 12a to 12n are the first DMA request signal and the second DMA, respectively.
Request signal to n-th DMA request signal input terminal, 13 is a base address register, 14 is a current address register, 15 is a temporary address register holding an address, 16 is a base word count register, 17 is a current word count register, and 18 is A random-word count register that holds the number of times DMA transfer is performed, 19a to 19n are base address register 13, current address register 14, temporary address register 15, base word count register 16, current word count register 17, and temporary word, respectively. The first DMA channel to the n-th DMA channel configured by the count register 18.

Next, the operation of the function-equipped DMA controller having the above configuration will be described. First of all,
If the DMA channels 19a to 19n are set in the single transfer mode and in the rotation priority order, the first DMA channel 19a becomes in service when the first DMA request signal is input. At this time, if there is no other DMA channel in service, one DMA operation is performed for one DMA request signal, the temporary address register 15 of the first DMA channel 19a is incremented by +1 or decremented by 1, and the temporary word At the same time as the count register 17 decreases by -1, the current address register 14 and the current word count register 17 are updated to the same value as the temporary address register 15 or the temporary word count register 17, respectively. The above operation is repeated until the temporary word count register 18 of the first DMA channel 19a becomes 0, and the service of the first DMA channel 19a ends.
By the way, while this first DMA channel 19a is in service, another DMA channel, for example, the second DMA channel 19b, the second DMA channel
When the request signal is input, this second DMA channel 19
b is also in service. Then, since the rotation priority is set, if the first DMA channel 19a is in the middle of a DMA operation, when the DMA operation is finished, and if it is waiting for the next DMA request, the second DMA channel is immediately sent. 19b executes the DMA operation, and the temporary address register 15, the temporary word count register 18, the current address register 14 and the calendar word count register 17 of the second DMA channel 19b are updated. Thus, even during one DMA channel service, the service can be received without waiting until the DMA service is completed, and the DMA operates in a multiplexed manner.

〔The invention's effect〕

As described in detail above, according to the DMA controller with a function capable of performing multiple operations according to the present invention, the base address register that holds the first address for independent DMA transfer and the base address register that is connected to the data bus A current address register that holds a value that is changed by 1 for each DMA transfer with respect to the value that is held by, and a temporary address register that holds the value held by the current address register by connecting to the address bus, A base word count register that holds the number of DMA transfers,
Connected to the data bus, the current word count register that holds a value that is reduced by 1 from the value that the base word count register holds for each DMA transfer, and the current word address register that is connected to the address bus and held by the current word address register By equipping each of the multiple DMA channels with a temporary word count register that holds the value being stored, even if one DMA channel is in service in single transfer mode, that channel can actually perform the DMA operation. Even if the I / O controller making the DMA service request has an overrun error, the other DMA channels can be in service during the idle period and can actually perform the DMA operation. Since there is no need for program control, the processing speed of the system is improved and There is an effect of, or the like can also be simplified.

[Brief description of the drawings]

FIG. 3 is a block diagram showing an embodiment of a DMA controller with a function capable of performing multiple operations according to the present invention. 1 ... Data bus, 2 ... Data bus buffer, 3 ...
Mode register, 4 ... Status register, 5 ... Command register, 6 ... Mask register, 7 ... Request register, 8 ... Priority determination circuit, 9 ... Address bus buffer, 10 ... Hold request signal line , 11
...... Address bus, 12a to 12n ...... Terminal, 13 ...... Base address register, 14 ...... Current address register, 15
...... Temporary address counter, 16 …… Base word count register, 17 …… Current word count register, 18 …… Temporary word count register, 19a
~ 19n ... 1st DMA channel ~ nth DMA channel.

Claims (1)

(57) [Claims] 1. Use in a microcomputer system
In the DMA controller, a base address register that holds the first address for independent DMA transfer and a value that is changed by 1 for each DMA transfer with respect to the value held by the base address register by connecting to the data bus To a data bus, a temporary address register that holds the value held by the current address register by connecting to the address bus, a base address count register that holds the number of DMA transfers, A current word count register that holds a value that is reduced by 1 from the value that the base word count register holds for each DMA transfer that is connected, and a current word address register that holds the current word address register when connected to the address bus Temporary word count register that holds the current value Preparative provided to each of the plurality of DMA channels, the DMA controller with multiple operational functions, characterized in that the rotating priority and each DMA channel of DMA controller programmed to single transfer mode.