JP2624989B2 - Data transfer control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device and, more particularly, to continuous data transfer control over a plurality of channels in a direct memory access controller having a plurality of channels. The present invention relates to a technology that is effective when applied to a communication control LSI that performs data transmission control.

[Conventional technology]

Direct memory as a data transfer control device to reduce the load on the processor in data transfer control
2. Description of the Related Art An access controller has been conventionally used, and this controller performs data transfer control between a memory and various input / output circuits on behalf of a processor by acquiring a right to use a bus from the processor.

The transfer method by the direct memory access controller generally requires a bus use right for each data transfer of one word, and returns the use right to the processor after the operation is completed. It is roughly classified into a burst method in which a plurality of words of data are continuously transferred, during which the processor takes a wait state. In this burst system, if the occupation period of the bus by the direct memory access controller is unlimitedly increased, the operation efficiency of the processor may be reduced. Therefore, it is desirable to limit the number of continuous transfer words.

By the way, since a general system uses a plurality of peripheral devices, the direct memory access controller has a plurality of channels and performs data transfer control by setting a transfer destination address and a transfer word number for each channel. However, in the related art, no means has been taken for data transfer control in each channel so as to have relevance to each other. For example, when data transfer control is performed via a channel allocated to a specific peripheral device, even if a data transfer request is made to another channel, the operation of the channel that is performing data transfer first Is completed, the right to use the bus is once abandoned, and then a new handshake interface for acquiring the bus right is performed.

Examples of the literature describing a direct memory access controller having a plurality of channels include “Hitachi Microcomputer Data Book 8 / 16-bit Microcomputer Peripheral LSI”, page 389, issued by Hitachi, Ltd. in September 1985. There is P442.

[Problems to be solved by the invention]

However, in a direct memory access controller having a plurality of channels, no means is provided for associating the data transfer control in each channel with each other, and the bus right acquisition control for each channel is completely performed. Independence means that every time data transfer control is transferred to another channel, an operation to relinquish the bus right and acquire a new bus right is required, thereby lowering the data transfer efficiency and lowering the system throughput. There was a problem of inviting.

In particular, according to the study of the present inventor, in a system in which related data must be transferred over a plurality of channels, for example, a system including a controller for communication control, data transmission / reception via a line control unit is performed. Control information and direct memory access required for control
It is necessary to read address information and the like necessary for data transfer control by the controller from the main memory,
In addition, since it is necessary to perform transmission processing according to the received content, various operations such as transferring various control information and transmission data from the main memory to the communication control controller and transferring received data to the main memory are performed. It has been found that there are frequent cases of association between the systems, and in such a case, if data cannot be transferred continuously over a plurality of channels, the throughput of the system will be significantly reduced.

An object of the present invention is to provide a data transfer control device capable of continuously performing data transfer over a plurality of channels and achieving improvement in data transfer efficiency.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of data transfer channels are provided, a burst number register for defining the number of data transfer words in each channel, a total burst number register for defining the number of continuous data transfer words over a plurality of channels, and a data transfer channel. In response to the possible state, control for acquiring the bus right is performed, and the number of continuous data transfer words in each channel is individually controlled based on the set value of the burst number register. And control means for maintaining the bus right for another channel in a state in which data transfer is possible until the set value of the burst number register is reached. At this time, the burst number register or the total burst number register can be configured to be rewritable.

In addition, the line control unit and central processing
When the data transfer control device is included in the communication control LSI including the unit, the data transfer control device can be connected to the line control unit by a dedicated data transfer bus.

(Operation)

According to the above means, the control means acquires the bus right in response to the state in which data can be transferred in the channel, and controls the maximum number of continuous data transfer words in each channel according to the set value of the corresponding burst number register. When receiving a state in which data transfer is possible in a plurality of channels, a series of data spanning a plurality of channels so as to maintain the bus right until the number of continuous data transfer words after acquiring the bus right reaches the maximum value set in the total burst number register. By controlling the number of words to be transferred and controlling the relinquishment of the bus right, continuous data transfer over a plurality of channels is enabled, thereby improving the data transfer efficiency.

In particular, by employing a rewritable burst number register or a total burst number register, the degree of freedom in continuous data transfer control over a plurality of channels is increased.

When the data transfer control device included in the communication control LSI is connected to the line control unit by a dedicated data transfer bus, data transfer between the line control unit and the outside of the LSI is controlled by access control of the data transfer control device. When performed, the common internal bus inside the communication control LSI is not occupied by the data transfer, and during such data transfer, the built-in central processing unit uses the common internal bus as necessary for communication protocol processing etc. This makes it possible to prevent this condition from significantly reducing the operating efficiency of the built-in central processing unit even if the frequency of data transfer for transmission / reception becomes extremely high due to the nature of the communication control LSI. I do.

〔Example〕

FIG. 1 is a system block diagram including a direct memory access controller which is one embodiment of a data transfer control device according to the present invention. A direct memory access controller (also simply referred to as DMAC) 1 shown in FIG. 1 is not particularly limited, but a communication control LSI 2 formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique. Built in.

Although not particularly limited, the communication control LSI 2 shown in FIG. 1 is coupled to a system bus 12 together with a main memory 3 for storing transmission / reception data and various parameters, a host processor 4 for controlling the entire system, and the like. A function module is configured to support data transmission control means and other controls when performing data communication with another communication function module forming a partner station.

 Here, the communication control LSI 2 will first be described overall.

The communication control LSI 2 includes a line controller 6 for performing a serial interface with a partner station via a transmission line TL and a reception line RL, a host interface 7 for interfacing with a host processor 4, a main memory 3, and the like, without using a host interface 7. DMAC1 for performing data transfer directly to the main memory 3 etc., various control data such as system constants required for data transmission control via the line control unit 6, and data transfer control by the DMAC1 RAM for rewritably storing various control information
(Random access memory) 8 and communication control LSI 2
CPU (Central Processing
Unit) 9 and a ROM (read only memory) 10 in which a communication protocol processing program for defining a data transmission control procedure in the line control unit 6 and other programs for controlling the entire communication control LSI are incorporated.
Are connected to the common internal bus 5 respectively.

The line control unit 6 is not particularly limited,
Bit synchronization and character synchronization are applied to the serial data received from the RL, the serial / parallel conversion of the data is performed, a predetermined operation for detecting a transmission error is performed, and a CPU 9 is executed in accordance with the type of the received data or the received frame. Is instructed to perform predetermined interrupt processing. When sending data, the data or frame to be sent is converted from parallel to serial,
The data is transmitted from the transmission line TL while adding a code for detecting a transmission error and the like while employing bit synchronization and character synchronization.

The host interface 7 includes a host processor 4
Issues commands to the communication control LSI2,
Used to read the status corresponding to the internal state of the.

The DMAC 1 performs data transfer control for storing received data or a predetermined field of a received frame processed by the line control unit 6 in the main memory 3, and transmits the data stored in the main memory 3. It controls the transfer to the line controller 6, and further controls the transfer of various parameters necessary for communication protocol processing, data for table configuration, and information for data transfer control by the DMAC 1 between the main memory 3 and the RAM 8. .

Although not particularly limited, the line control unit 6 and the main memory 3
A data transfer based on the control of the DMAC1 performed between the DMAC1 and the DMAC1 and the line control unit 6
11 is used. Thereby, when data transfer between the line control unit 6 and the main memory 3 is performed by the access control of the DMAC 1, the common internal bus 5 is not occupied by the DMA transfer, and during the DMA transfer, the CPU 9 The common internal bus 5 can be used as needed for communication protocol processing.

Between the line controller 6 and the DMA transfer bus 11,
Although not particularly limited, first-in-first-
An out-format data buffer (not shown) is provided to absorb or buffer the difference between the data transfer speed under the control of the DMAC 1 and the data transmission / reception speed by the line control unit 6.

In the case where such a communication control LSI 2 employs, for example, HDLC (High Level Data Link Control) sequence control means, the line control unit 6 decodes data or frames supplied thereto, While processing of the information contained in the address and the control field contained therein is advanced, the information constituting the frame, that is, the information of the received frame or the information to be transmitted transferred from the main memory 3 via the DMAC 1 is transmitted to the first The data is stored in an in-first-out type data buffer (not shown).

At this time, the line control unit 6 gives various interrupts to the CPU 9 according to the address and the information included in the control field. The CPU 9 generates a vector corresponding to the type of the interrupt at that time and branches the control procedure. For example, when the information frame is received, the frame check sequence is compared with the calculation result for error detection.
The DMAC1 is activated, and the information field of the received data stored in the data buffer (not shown) is transferred to the main memory 3 via the DMAC1. In the case of transmission of an information frame, an information field taken into a data buffer (not shown) via the DMAC 1 includes an address field, a control field, a frame start flag,
A frame is created by adding a frame check sequence and a frame end flag, and this frame is transmitted from the line control unit 6.

 Next, the details of the DMAC 1 will be described.

The DMAC 1 according to the present embodiment includes a zeroth channel CH ₀ for transferring data received by the line control unit 6 to the main memory 3,
A first channel CH ₁ for transferring transmission data from the main memory 3 to the line control unit 6 and a second channel CH ₂ for transferring data between the main memory 3 and the RAM 8 are provided.

As a data transfer control register corresponding to the 0th channel CH ₀ , a status register SR ₀ indicating whether data transfer is possible in the channel by an enable bit or a disable bit, a byte count register BC ₀ in which the number of data transfer bytes is set, There are provided an address register AR ₀ in which the transfer destination start address is stored, and a burst number register BR _{0 in} which the number of continuous data transfer bytes in the 0th channel in the burst mode is set. Similarly the data transfer control registers corresponding to the first channel CH ₁ is
A status register SR ₁ indicating whether data transfer is possible or not in the channel by an enable bit or a disable bit, a byte count register BC ₁ for setting the number of data transfer bytes, an address register AR ₁ for storing a transfer source head address, a burst mode. continuous data transfer byte count in the first channel CH ₁ is the burst number register BR ₁ is set according to, further, the data transfer control registers corresponding to the second channel CH _2, the mode register MR ₂ indicating the data transfer direction A status register SR ₂ indicating whether data transfer is possible in the channel by an enable bit or a disable bit, a byte count register BC ₂ in which the number of data transfer bytes is set, and an address where a transfer source start address and a transfer destination start address are stored. register AR _2, Ba Continuous data transfer byte count in the second channel CH ₂ by strike mode is a burst number register BR ₂ is set.

The CPU 9 sets data in the various data transfer control registers provided corresponding to the channels CH _{0 to} CH ₂ based on an interrupt from the line control unit 6 or a command given from the host processor 4.

When the enable bits are set in the status registers SR ₀ , SR ₁ , SR ₂ , the corresponding channels CH ₀ , CH ₁ , CH
Channel request signals CREQ ₀ , CREQ ₁ , CRE corresponding to ₂
Q ₂ is asserted.

The set values of the byte count registers BC ₀ , BC ₁ , and BC ₂ corresponding to the respective channels CH ₀ , CH ₁ , and CH ₂ are decremented by a decrementer (not shown) each time a 1-byte data transfer operation is performed on the corresponding channel. Bicount register BC ₀ ,
When BC ₁ and BC ₂ are _decremented and returned to the clear state, the enable bits of the corresponding status registers SR ₀ , SR ₁ and SR ₂ are reset, and the corresponding channel request signal CREQ ₀ , CREQ ₁ and CREQ ₂ are negated.

The set values of the burst number registers BR ₀ , BR ₁ , BR ₂ are compared with the value of a burst number compare register (not shown). This burst number compare register is cleared by the start of the data transfer operation in the corresponding channel, and is cleared by one.
The value is incremented each time byte data is transferred. When the value of the burst number compare register (not shown) matches the value of the corresponding burst number register, the corresponding byte counter register has not reached the clear state and the corresponding channel request signal CREQ ₀ , CREQ ₁ , CREQ
_{When 2} holds the asserted state, the channel request signal is once negated and then reasserted.

The address registers AR ₀ , AR ₁ , and AR ₂ hold the next address by adding the set value by an incrementer (not shown) for each one-byte data transfer operation in the corresponding channel.

The channel request signals CREQ ₀ , CREQ ₁ , CREQ ₂ are each supplied to the transfer control unit ACONT. This transfer control unit ACONT
Any _{one of} channel request signals CREQ ₀ , CREQ ₁ , CREQ ₂
When one of them is asserted, the bus request signal BREQ is asserted in response to this request to request the host processor 4 to release the bus right. After completing the current memory cycle, the host processor 4 asserts the bus acknowledge signal BACK to relinquish the bus right. As a result, the transfer control unit ACONT that has acquired the bus right asserts one of the channel acknowledge signals corresponding to each channel and instructs a predetermined channel to start a data transfer operation. At this time, when a plurality of channel request signals are asserted, priority control is performed according to early or late timing of the assertion, and a channel acknowledge signal is asserted for a channel with a higher priority.

The transfer control unit ACONT enables continuous data transfer over a plurality of channels while maintaining the bus right once obtained. That is, a total burst number register TBR for specifying the number of continuous data transfer bytes over a plurality of channels is provided. The CPU 9 initializes the total burst number register TBR with the total burst number. This set value is compared with the value of a not-shown total burst number compare register. The total burst number compare register is cleared in response to the transfer control unit ACONT acquiring the bus right and causing any of the channels to start a data transfer operation, and thereafter is incremented every time one byte of data is transferred. After acquiring the bus right, the transfer control unit ACONT transmits all the channel request signals CREQ ₀ , CR
The bus right is abandoned only when EQ ₁ and CREQ ₂ are negated, and when the value of the total burst number register (not shown) matches the total burst number register TBR.

Therefore, when one channel request signal is asserted, the value of the burst number compare register (not shown) in the corresponding channel matches the set value of the corresponding burst number register, or the byte count corresponding to the channel When the register is cleared to 0, the bus right is relinquished. When a plurality of channel request signals are asserted, the value of the burst number compare register (not shown) in the channel on which the data transfer operation is first started based on the priority control corresponds to the corresponding burst number register BR ₀ , BR ₁ , BR Matches the set value of ₂ ,
Or the byte count register BC corresponding to the channel
_0, is cleared to BC _1, BC ₂ is 0, even if the channel request signal of the channel is negated, the asserted state is held by a channel request signal in the asserted state in the bus request signal BREQ other channel, as follows The operation is shifted to the data transfer operation in the channel of. Until the value of the total burst number compare register (not shown) matches the set value of the total burst number register TBR, a series of data transfer operations over a plurality of channels is permitted during one bus right acquisition period.

Next, a series of data transfer operations over a plurality of channels by the DMAC 1 will be described.

When the communication control LSI 2 receives data from the receiving line RL, the received data is converted into parallel data by the line control unit 6 and stored in an internal data buffer (not shown). Occurs. Thus CPU9 sets various control information necessary for data transfer control via the 0th channel CH ₀ of DMAC1. That is, sets the number of data transfer bytes byte count register BC _0, and stores the destination start address in the main memory 3 in the address register AR _0, and sets the enable bit in the status register SR _0. The operation of setting the number of continuous data transfer byte in the 0th channel CH ₀ to burst number register BR ₀ is not particularly limited, is done at system startup, the value is kept constant.

When performing data transmission from the transmission line TL of the communication control LSI 2, the host processor 4 stores data to be transmitted in the main memory 3 in advance, and then gives a command for instructing data transmission to the CPU 9. CPU9 is In executing this command, sets various control information necessary for data transfer control via the first channel CH ₁ of DMAC1. That is, sets the number of data transfer bytes byte count register BC _1, and stores the transfer source head address in the main memory 3 to the address register AR _1, further sets the enable bit in the status register SR _1. still,
Operation for setting the number of consecutive data bytes transferred in the first channel CH ₁ to the burst number register BR ₁ is not particularly limited, is done at system startup, the value is kept constant.

Various parameters or control information necessary for data transmission / reception via the line control unit 6 are stored in the RAM 8 and the main memory 3.
In the case of transferring data between them, the host processor 4 gives a command necessary for the data transfer to the CPU 9 in advance. CPU9
The order to execute this command, sets various control information necessary for data transfer control via a second channel CH ₂ of DMAC1. That is, the byte count register BC
₂ to the number of data transfer bytes and mode register MR ₂ sets the data indicating the data transfer direction, and stores the transfer source head address and the transfer destination address in the address register AR _2, further enable the status register SR _2, Set a bit. The operation of setting the number of continuous data transfer byte in the second channel CH ₂ to the burst number register BR ₂ is not particularly limited, is done at system startup, the value is kept constant.

Total burst number register TBR included in transfer control unit ACONT
Although not particularly limited, data corresponding to 8 bytes is set when the system is started.

Here, the following description of the operation of the case where three channels CH ₀ to CH ₂ in the data transfer operation is instructed in turn by the status register SR ₀ to SR after the other enable bit to ₂ each are set Center.

For example, assuming that the setting operation of the enable bit is performed in the order of the status registers SR ₀ , SR ₁ , and SR ₂ , the channel request signals CREQ ₀ , CREQ ₁ , CR
EQ ₂ is asserted given to the transfer control unit ACONT with. Transfer control unit ACONT accordingly requests the bus to the host processor 4 asserts the bus request signal BREQ to the time t ₀ of Figure 2. When the host processor 4 with respect to this request to relinquish the bus by asserting the bus acknowledge signal BACK in the time t ₁ of FIG. 2, the transfer control unit ACONT the channel request signal CREQ _0, CREQ _1, assertion of CREQ ₂ Based on the priority control according to the early or late timing, a channel acknowledge signal CACK ₀ corresponding to the initially asserted channel request signal CREQ ₀ at that time is asserted, so that the data received by the line control unit 6 becomes the 0th channel. starts transferred to the main memory 3 to the time t ₂ of FIG. 2 through the CH _0.

At this time, data corresponding to 7 bytes is set in the byte count register BC ₀ of the 0th channel CH ₀ ,
Assuming that data corresponding to 3 bytes is set in the burst number register BR ₀ , the channel is used when the received data of the line control unit 6 is transferred to the main memory 3 by 3 bytes using the 0th channel CH _0. Request signal CR
EQ ₀ is negated, the channel acknowledge signal CACK ₀ receives also data transfer operation in the 0th channel CH ₀ by being negated is ended once again channel for the remainder of the data transfer in the channel CH ₀ Request signal CREQ ₀ is asserted.

After the transfer control unit ACONT has acquired the bus at time t _1, when the data transfer is started in the 0-channel CH _0, 1
Every byte data transfer, the total burst number compare register (not shown) is sequentially incremented from the clear state,
The transfer controller ACONT determines whether this value reaches the value of the total burst number register TBR. When the channel request signal CREQ ₀ is once negated as described above, since the not-shown total burst number compare register has not reached the set value of the total burst number register TBR of 8 bytes, the transfer control unit ACONT The channel acknowledge signal C corresponding to the channel request signal CREQ ₁ is granted by giving priority to the channel request signal CREQ ₁ by priority control without abandoning the bus right.
Assert ACK ₁ . Thus, the 0 data transfer channel first channel CH ₁ following the CH ₀ second
It is started from the time t ₃ of FIG.

In this case the byte count register BC ₁ of the first channel CH ₁ is set data to comply to 3 bytes, when the burst number register BR ₁ and data to comply to the 2 bytes are set, data to be transmitted this Line control unit 6 from main memory 3 using channel ₁
When only 2 bytes have been transferred, the channel request signal CREQ ₁ is once negated, and in response to this, the channel acknowledge signal CACK ₁ is also negated, thereby terminating the data transfer operation in the first channel CH ₁ once, and again A channel request signal CREQ ₁ is asserted for the remaining data transfer in one channel CH ₁ .

When the channel request signal CREQ ₁ is once negated in this manner, the total burst number compare register (not shown) is the set value of the total burst number register TBR of 8
Since the byte has not been reached, the transfer control unit ACONT does not relinquish the bus right at that time, but grants priority to the channel request signal CREQ ₂ by priority control, and then issues a channel acknowledge signal CACK corresponding to the channel request signal CREQ ₂ Assert ₂ . Thus, the 0 data transfer channel CH ₀ and the second channel CH ₂ following the first channel CH ₁ is started at time t ₄ of Figure 2.

At this time, if it is assumed that data corresponding to one byte is set in the byte count register BC ₂ in the second channel CH ₂ and data corresponding to _two bytes is set in the burst number register BR ₂ , the second channel CH ₂ Is used to transfer 1-byte data between the main memory 3 and the RAM 8, the channel request signal CREQ ₂ is negated.
CK ₂ also the data transfer operation in the channel CH ₂ is terminated by being negated.

When the channel request signal CREQ ₂ is negated in this manner, the transfer control unit ACONT transmits the bus right at that time because the total burst number compare register (not shown) has not reached the set value of the total burst number register TBR of 8 bytes. Without giving up, the priority is re-acknowledged for the channel request signal CREQ ₀ by the priority control, and the channel acknowledge signal CACK ₀ is asserted as in the first case. Thereby, the 0th channel CH ₀ , the 1st channel CH ₁ ,
And the second channel CH ₂ again after the _second channel CH ₂
Data transfer in is started at time t ₅ of FIG. 2.

When the current data transfer in the 0th channel CH ₀ is performed by 2 bytes, the value of the total burst number compare register (not shown) reaches 8 bytes which is the set value of the total burst number register TBR, so that the transfer control unit ACONT The acknowledgment signal CACK ₀ is negated to stop the data transfer operation of the third byte in the channel ₀ , and
At the time t ₆ in the figure negates the bus request signal BREQ to temporarily relinquish the bus. Thus, continuous data transfer across multiple channels based on the bus right acquired at time t ₁ is completed is 8 bytes defined by set values of all the burst number register TBR.

When such bus was abandoned at time t ₆ in the, in the byte count register BC ₀ in the 0-channel CH ₀ remainder value responsive to 2 bytes, Also, the first channel CH ₁
Since a value corresponding to one byte remains in the byte count register BC ₀ of the channel request signal CR 0
EQ ₁ and CREQ ₁ maintain the asserted state.
Accordingly, the transfer control unit ACONT the time t ₆ asserts again bus request signal BREQ to the time t ₇ after abandoning the bus to a bus request to the host processor 4. When the host processor 4 with respect to this request to relinquish the bus by asserting the bus acknowledge signal BACK in the time t ₈ in Figure 2, the transfer control unit ACONT channel acknowledge signal to comply with the channel request signal CREQ ₀ in accordance with the priority control Assert CACK ₀ , which causes time t _{8 in} FIG.
Data transfer is initiated via the 0th channel CH ₀ again. The data transfer on the 0th channel CH ₀ is 2
When performed bytes, result byte count register BC ₀ is cleared, the data transfer in the zeroth channel CH ₀ is terminated in response to the channel request signal CREQ ₀ is negated. Channel request signal CREQ
₀ There are channel request signal CREQ ₁ of the first channel CH ₁ when negated asserted, and since the value of the total number of bursts compare register (not shown) has not reached the value of total burst number register TBR, transfer Control unit A
CONT initiates the data transfer from the time t ₁₀ gives it priority to the channel request signal CREQ ₁ without abandoning the bus to the first channel CH _1. This first channel C
When data transfer in H ₁ is carried out 1 byte, the result byte count register BC ₁ is cleared, the data transfer is completed in the first channel CH ₁ in response to the channel request signal CREQ ₁ is negated . According to the present embodiment, the channel request signal CREQ ₁ is negated, a channel request signal being asserted is eliminated, the transfer control unit ACONT accordingly at time t ₁₁ negates the bus request signal BREQ Abandon the bus.

According to the above embodiment, the following effects can be obtained.

(1) The DMAC 1 acquires the bus right in response to the data transfer enabled state in each of the channels CH ₀ , CH ₁ , CH ₂ , that is, the set state of the enable bit, and the individual channels CH ₀ , CH ₁ , CH 2
₂ is controlled in accordance with the set values of the corresponding burst registers BR ₀ , BR ₁ , BR ₂ , and when receiving data transfer enabled status on a plurality of channels, the number of continuous data transfer words after acquiring the bus right is reduced. By controlling the number of words in a series of data transfer across multiple channels and controlling the relinquishment of the bus, multiple channels can be maintained by maintaining the bus right until the maximum burst number register TBR is reached. And data transfer efficiency can be improved by enabling continuous data transfer over a network.

(2) In a system in which related data must be transferred over a plurality of channels including a communication control LSI as in the present embodiment, control information necessary for data transmission / reception control via the line control unit 6 It is necessary to read address information and the like necessary for data transfer control from the main memory 3 and also to perform transmission processing according to the received contents. In some cases, there is an association between the operations of transferring data from the memory 3 to the RAM 8 and transferring the received data to the main memory 3, and in such a case, continuous operation is performed over a plurality of channels as in this embodiment. If data transfer can be performed in a specific manner, the throughput of the system can be significantly improved. In this case, the DMAC1 occupies the bus only for the period of transferring the maximum number of bytes set in the total burst number register TBR, and does not hold the bus right indefinitely. Does not decrease.

(3) In particular, rewritable burst number register BR ₀ .about.B
By adopting the R ₃ and the total number of bursts register TBR,
The number of continuous data transfer words over a plurality of channels can be arbitrarily changed, and the flexibility of the system can be increased. For example, the burst number register BR ₀ .about.B
Respect R _2, to prevent reception overrun can be set larger the number of bursts 0th channel CH ₀ for the received data transfer. Further, it is sufficient to set a number of bursts number of first channel CH ₁ of the transmission data transfer in a system such as underrun transmission becomes critical.

(4) Performed between the line control unit 6 and the main memory 3
For data transfer under the control of DMAC1, the line controller 6 and DMAC1
When the DMA transfer dedicated bus 11 is used, the common internal bus 5 is not occupied by the DMA transfer during such data transfer, and during the DMA transfer, the CPU 9 switches the common internal bus 5 as necessary for communication protocol processing. Can be used. Therefore, even if the frequency of data transfer by the DMAC1 becomes extremely high due to the nature of the communication control LSI, it is possible to prevent this state from becoming an obstacle to the communication protocol processing by the CPU 9, and to contribute to the improvement of the system efficiency as described above. it can.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the number of channels is three and the number of all burst number registers is one. However, the present invention is not limited to this, and the number of channels and the number of all burst number registers can be changed as appropriate. For example, when the number of channels is set to 10, channels 0 to 4 are placed under the control of the first total burst number register, and channels 5 to 9 are placed under the control of the second total burst number register. Can be put down.

In the above embodiment, the burst number register and the total burst number register are configured to be rewritable. However, the rewriting timing is not limited to when the system is started, and can be appropriately performed when setting control information for a channel. The data holding function of the register may be nonvolatile or fixed.

Further, in the above embodiment, the priority control for each channel request signal is performed based on the early or late of the assert timing of those signals, but the priority control is performed based on the priority set in advance for each channel. Is also good.

In the above description, one-chip communication control, which is a field of application in which the invention made by the inventor is mainly used, is described.
Although the description has been given of the case where the present invention is applied to an LSI, the present invention is not limited to this, and may be applied to various semiconductor integrated circuits such as a single-chip microcomputer as a single DMAC. The present invention can be applied to a condition having a data transfer control function having at least a plurality of channels.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, while controlling the number of continuous data transfer words in each channel based on the set value of the burst number register, data transfer is possible until the number of continuous data transfer words after acquiring the bus right reaches the set value of the total burst number register. By maintaining the bus right for the other channels in the state, there is an effect that the data transfer efficiency can be improved by enabling continuous data transfer over a plurality of channels.

In addition, by employing a rewritable burst number register and a total burst number register, the number of continuous data transfer words over a plurality of channels can be arbitrarily changed, and the flexibility of the system can be increased. This has the effect.

When the data transfer control device is included in the communication control LSI having the line control unit and the central processing unit, and the data transfer control device is connected to the line control unit by a dedicated data transfer bus, the characteristics of the communication control LSI Even if the frequency of transmission / reception data transfer by the data transfer controller becomes extremely high, this
It is possible to prevent the processing unit from obstructing communication protocol processing or the like, thereby contributing to an improvement in system efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system block diagram including a direct memory access controller which is an embodiment of a data transfer control device according to the present invention, and FIG. 2 is a direct memory access controller described above. 5 is a time chart for explaining a series of data transfer operations over a plurality of channels according to the first embodiment. 1 ... DMAC, 2 ... Communication control LSI, 3 ... Main memory, 4 ... Host processor, 5 ... Common internal bus, 6
…… Line control unit, 7… Host interface, 8…
RAM, 9 CPU, 10 ROM, 11 Bus dedicated to DMA transfer
12 System bus, CH ₀ , CH ₁ , CH ₂ … Channel, SR ₀ , S
R ₁ , SR ₂ … status register, BC ₀ , BC ₁ , BC ₂ … byte count register, AR ₀ , AR ₁ , AR ₂ … address register, BR ₀ , BR ₁ , BR ₂ … burst number register , MR ₂ ... mode register, CREQ ₀ , CREQ ₁ , CREQ ₂ ... channel request signal, CACK ₀ , CACK ₁ , CACK ₂ ... channel acknowledge signal, ACONT ... transfer control unit, BREQ ... bus request signal, BACK …… Bus acknowledge signal.

Claims (3)

(57) [Claims] A plurality of data transfer channels; a burst number register for defining the number of data transfer words in each channel; a total burst number register for defining a continuous data transfer word number over a plurality of channels; In response to the state in which data transfer is possible, control is performed to acquire a bus right, the number of continuous data transfer words in each channel is controlled based on the set value of the burst number register, and continuous data transfer after the bus right is acquired. Control means for maintaining a bus right for another channel in a data transferable state until the number of words reaches a value set in a total burst number register. 2. The data transfer control device according to claim 1, wherein the burst number register or the total burst number register is configured to be rewritable. 3. A communication control LSI comprising a line control unit and a central processing unit, wherein the line control unit is connected to the line control unit by a dedicated data transfer bus. The data transfer control device according to the item.