JP2633852B2 - Data processing device - Google Patents

Description

The present invention relates to a serial data communication control technique, and further to a control technique for storing a group of data, such as a frame, in a buffer memory so that a break can be recognized. The present invention relates to a technique effective when applied to a data processing device having a serial channel and a direct memory access function for supporting transfer control of serial data by a high-level data link controller method.

(Prior art)

A serial channel or serial interface controller for transmitting bit-serial information between processors, such as a start-stop synchronization method, a binary synchronous communication method, a high-level data link control (hereinafter simply referred to as HDLC) method, and a local area network control method For example, in the HDLC system, data is transmitted and received in units called frames. In such a case, if the data transfer rate is high or the amount of data to be transferred for each frame is large, a direct memory access control method may be used to transfer data between a rewritable memory such as a buffer memory and a serial channel. It is desirable to perform the data transfer control in order to improve the system efficiency.

By the way, when transmitting / receiving data is transferred for each frame, a frame delimiter can be recognized for post-processing of a target of a software communication protocol such as a control field and an error check field included in an equal frame. In such a case, a frame switching process for storing transmission / reception data in a buffer memory is required.

The present inventors reset the direct memory access control by requesting an interrupt to the central processing unit in response to detecting the end flag indicating that the serial channel indicates the end of the frame, as the frame switching process. The method was discussed. That is, when the control flow of the central processing unit branches to a predetermined interrupt routine, a command instructing an operation of writing a delimiter signifying the end of the frame into a predetermined area of the buffer memory or a next frame is used. A command for changing the transfer destination address is issued to the direct memory access controller to execute the frame switching process.

[Problems to be solved by the invention]

According to the study of the present inventors, in the above-described method of performing the frame switching process by interruption to the central processing unit, the number of execution cycles of various commands for resetting the direct memory access control is increased, and the frame switching is performed. There is a possibility that the predetermined processing cannot be completed within the given time, and the load on the central processing unit cannot be reduced.

Further, according to the study of the present inventors related thereto, since both the direct memory access controller and the central processing unit function as a bus master, when they are configured as separate chips, the bus arbitration is performed. It takes time, and the interrupt processing for the above-described frame switching processing is also delayed accordingly, and it has been clarified that the above problem is exacerbated.

An object of the present invention is to provide a direct memory access control method for storing a group of data to be exchanged in a memory by a direct memory access control method so that the storage location can be switched directly to a group of data. It is to provide a data processing device enabled by a memory access controller.

Another object of the present invention is to increase the speed of processing for storing a group of data to be exchanged in a memory by a direct memory access control method so that a segment of a group of data to be exchanged can be recognized. The object of the present invention is to provide a data processing device having:

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a representative embodiment of the present invention is a memory (DM) interconnected to a bus (EBUS, IBUS).
And a central processing unit (CPU), a direct memory access controller (DMAC), and a serial channel (SIC).
Is the memory (DM) via the bus (EBUS, IBUS)
The serial channel (SIC) is a serial interface controller for transmitting information bit-serially to and from an external device, the serial channel (SIC) being a serial interface controller; The information transmission between the channel (SIC) and the external device is performed in units of a frame as a group of information, and the frame is capable of transmitting data communication including an end flag indicating the end of the frame. The memory (DM) includes a plurality of storage destination areas (BA1... BAn) for storing data of the frame, the serial channel (SIC) and the direct memory access controller (DMAC). Between the above bus (EB
A signal line (CL) is provided separately from the US and IBUS. When the serial channel (SIC) recognizes the end flag indicating the end of the frame of the bit serial information transmission, the signal line (CL) The serial channel (SIC) notifies the recognition to the direct memory access controller (DMAC) via the direct memory access controller (DMAC) via the bus (EBUS, IBUS). When transferring a group of information from the serial channel (SIC) to the memory (DM) and storing the information, the storage switching process of the plurality of storage destination areas (BA1... BAn) of the memory (DM) is performed. Features (see FIGS. 1 and 2).

(Operation)

According to the invention having the features described above, the serial channel (SI
When C) recognizes the end flag indicating the end of the frame of the bit serial information transmission, it is provided between the serial channel (SIC) and the direct memory access controller (DMAC) separately from the bus (EBUS, IBUS). Signal line (C
L) through the end channel recognition information via the serial channel (S
Direct memory access controller (DMA) from IC
C) will be notified. In response to this notification, the direct memory access controller (DMAC) sets the bus (EBUS, IBU
Memory (DM) from serial channel (SIC) via S)
When a group of information is transferred and stored in the memory (DM), a storage switching process of a plurality of storage destination areas (BA1... BAn) of the memory (DM) is executed.

Therefore, the end flag recognition information of the end of transmission of the frame information is notified from the serial channel (SIC) to the direct memory access controller (DMAC) via the dedicated signal line (CL) without using the bus (EBUS, IBUS). You.

As a result, to notify the end flag recognition information,
Generation of a request signal (request signal) for use of the bus (EBUS, IBUS) and an acknowledgment signal (acknowledge signal) (ie,
This eliminates the need for bus use arbitration, and makes it possible to execute high-speed storage switching processing for a plurality of storage destination areas (BA1... BAn) of memos (DM).

〔Example〕

FIG. 1 is a block diagram showing a microcomputer which is one embodiment of a data processing device according to the present invention. The microcomputer MCU shown in FIG. 1 is a so-called single-chip microcomputer formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique.

1 is coupled to an external bus EBUS such as a system bus to which a rewritable memory DM such as a RAM (random access memory) is connected, although not particularly limited. ing. Although not particularly limited, this microcomputer MCU includes a central processing unit CPU, a direct memory access controller DMAC, and a serial channel SIC.
Each is representatively shown coupled to an internal bus IBUS.

The serial channel SIC is a serial interface controller for transmitting information bit-serial with an external device (not shown), and is not particularly limited. Asynchronous mode, binary synchronous communication mode, HDLC mode, local area network The control method is supported to be switchable. The transfer data format in the HDLC system is a unit of a frame as a group of information. For example, one frame includes a start flag, an address field, and a software protocol such as transferring data again if an error occurs. This is achieved by the target control field, the information field that is the substantial data, the CRC error check field, and the end flag.

For example, when the HDLC method is selected, the serial channel SIC supports a control signal and a control procedure necessary for exchanging information in a bit-serial format in units of frames, detects a flag pattern, and detects an address field. , An input / output operation of data through a comparison of generation of a check code, and the like.

The direct memory access controller DMAC,
A controller having a chain function for directly controlling the transfer of information to be exchanged via EBUS and IBUS at least between the memory DM and the serial channel SIC.

The central processing unit CPU has general versatility capable of coping with various communication control protocols when data is transferred from the serial channel SIC to the memory DM in units of frames via the direct memory access controller DMAC. For example, its versatility means that when the HDLC method is selected for the serial channel SIC, it flexibly handles the type of software communication protocol such as the control field included in a frame that is the transfer data format. It means you can do it.

In FIG. 1, CL is a signal line for notifying the direct memory access controller DMAC when the serial channel SIC recognizes the end flag indicating the end of the frame. When the end of the received frame is notified to the direct memory access controller DMAC by the signal line CL, the direct memory access controller DMAC sends the memory D from the serial channel SIC to the memory D.
When the data is transferred to M for each frame so that the delimiter can be recognized, the frame switching processing is controlled by itself.
Such a frame switching process is, for example, an operation of writing a delimiter signal indicating the end of the frame in a storage destination area for the frame in the memory DM or an operation of changing a transfer destination address of the next frame. is there.

Next, the frame switching process will be described in relation to the chain function of the direct memory access controller DMAC.

Here, the chain function means that a relatively large number of relatively small buffer areas are prepared on a buffer memory such as the memory DM, and these are successively connected so that they can be identified by a descriptor functioning as a pointer, so that data is stored in blocks. This is a function that can be stored in

When a detailed example of this chain function on the basis of FIG. 2, on the memory DM, a plurality of buffer areas BA ₁ to BAn having a predetermined storage procedure, the descriptors DD ₁ to DDn, 1 pair 1 corresponds in each set, in which are successively identified linked to each buffer area BA ₁ to BAn. Each descriptor DD ₁ to DDn is first pointer PNT1, second pointer PNT
2, and an instruction column DES. The first pointer PNT1 describes a head address of a buffer area that can store one frame of received data and corresponds to a descriptor including the pointer, and the second pointer PNT2 describes a description including the pointer. The start address of the memory area in which the descriptor following the child is set is described. In the instruction column DES, a data delimiter signal indicating whether or not the reception data has ended in the buffer area indicated by the descriptor included therein is described.

Each buffer areas BA ₁ to BAn, access to the descriptor DD ₁ to DDn is the direct memory access controller DMAC is performed. When the serial channel SIC receives data transfer from the outside in a frame unit by the HDLC method, the direct memory access controller DMAC delimits the received data for each frame through reference to the descriptor and writing of a data delimiter. Then, they are stored in the buffer area in such a way that they can be identified one after another.

An example of a procedure for storing received data composed of a plurality of frames using the descriptor will be described. First, a descriptor corresponding to an unused buffer area is first, and a series of descriptors corresponding to the number of transfer frames are described. Describes the start address of the memory area in which the next following descriptor is set in each second pointer included in. For example, if the descriptor corresponding to the unused buffer space and DD _1, the second pointer PNT2 of the descriptor DD ₁ describes the start address of the next descriptor DD _2, the second descriptor DD ₂ describes the start address of the next descriptor DD ₃ is a pointer PNT2, hereinafter, they are processed similar description for each second pointers included in a series of descriptors number corresponding to the number of transfer frames. Such initialization can also be performed by the central processing unit CPU.

When performing frame transfer by the direct memory access controller DMAC, first, the first descriptor (DD
_The direct memory access controller DMAC refers to the data of the first pointer PNT1 included in ₁ ), and stores the data of the first frame sequentially from the reference address data in the buffer area (BA ₁ ). The serial channel S
When the IC detects the end flag in the first frame, the end of the received frame is notified to the direct memory access controller DMAC via the signal line CL. Then, the direct memory access controller DMAC describes the data delimiter signal in the instruction column DES included in the _first descriptor (DD ₁ ), and further writes the second pointer PNT2 in the _first descriptor (DD ₁ ). With reference to the described address data, the head address data of the next buffer area (BA ₂ ) is read from the first pointer PNT1 in the next descriptor (DD ₂ ). In this way, the direct memory access controller DMAC uses the central processing unit CPU
The frame switching process is performed at high speed without the need for intervention.

Next, when data relating to the next frame is transferred,
As described above, the direct memory access controller DMAC sequentially transfers the data of the second one frame to the buffer area based on the address data obtained from the first pointer PNT1 in the next descriptor (DD ₂ ) in the frame switching process. and stores it in the (BA _2). Thereafter, the same processing is performed until the last frame, and a series of data is divided into frames and stored in the memory DM in an identifiable manner.

According to the present embodiment, after a series of data is stored in the memory DM, processing for a control field included in each frame is executed by the central processing unit CPU. At this time, since the central processing unit CPU has general versatility capable of processing various communication control protocols for control fields and the like, it can flexibly cope with various HDLC schemes that can be selected by the serial channel SIC.

According to the above embodiment, the following operation and effect can be obtained.

(1) When the serial channel SIC detects an end flag in a frame, the end of the received frame is notified by the direct memory access controller DM via the signal line CL.
Directly notified to the AC, the direct memory access controller DMAC describes the data delimiter signal in the instruction column DES included in the descriptor based on the notification, and is further described in the second pointer PNT2 included in the descriptor. Referring to the address data, the first pointer PN in the next descriptor
By reading the first dress data of the next buffer area from T1, the frame switching process can be executed at high speed without requiring the intervention of the central processing unit CPU. Therefore, the frame switching process can be performed at a remarkably high speed as compared with the case where the frame switching process is handled by an interrupt process for the central processing unit CPU.

(2) In particular, when the serial channel SIC and the direct memory access controller DMAC are included in the same chip, they always operate synchronously. Therefore, the reception provided from the serial channel SIC to the direct memory access controller DMAC via the signal line CL is performed. No special acknowledgment signal is required for the end notification of the frame, so that the frame switching process can be performed at higher speed.

(3) According to the effects (1) and (2), a large number of relatively small buffer areas are prepared in the buffer memory, and these are successively connected so that they can be identified by a descriptor functioning as a pointer. Data frames are transferred using a direct memory access control method that has a chain function that enables data to be stored in blocks, thereby maximizing the intent to deal with a higher data transfer rate. be able to.

(4) Since the central processing unit CPU has general versatility capable of processing various communication control protocols for control fields and the like, it can flexibly cope with various HDLC schemes that can be selected by the serial channel SIC. . Therefore, the processable range is remarkably wider than that in which a controller dedicated to a certain communication control protocol is built in instead of the general-purpose central processing unit CPU.

(5) A serial channel SIC supporting at least the HDLC method, a direct memory access controller DMAC having a chain function for directly controlling the exchange of information to be exchanged between the memory DM and the serial channel SIC, and a direct memory access controller A general-purpose central processing unit capable of coping with various communication control protocols when transferring data from the serial channel SIC to the memory DM via the DMAC to the memory DM frame by frame is formed on one semiconductor substrate, and a single chip with a communication function is formed. By configuring a microcomputer, the direct memory access controller and the central processing unit, which can both function as a bus master, are configured on the same chip, so the time required for bus arbitration is configured on separate chips. Frame switching In addition, the speed of the communication control process can be improved as a whole, such that a group of data is separated and stored in the memory by the direct memory access control method, including the data processing.

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the embodiments, and various modifications can be made without departing from the gist of the invention.

For example, when the serial channel recognizes data indicating the end of a frame as a group of information to be exchanged,
As for the configuration in which a signal line for notifying the recognition to the direct memory access controller with a chain function is provided, the serial channel and the direct memory access controller do not have to be included in the same chip as in the above embodiment. In this case, if the serial channel and the direct memory access controller operate asynchronously with each other, it is necessary to provide the serial channel with an acknowledgment signal for the end notification such as the received frame.

Also, a direct memory access controller having a serial channel, a chain function, and a general-purpose central processing unit capable of coping with various communication control protocols when transferring data from the serial channel to the memory through the direct memory access controller to the memory frame by frame. In a configuration in which the device and a single-chip microcomputer with a communication function are formed on one semiconductor substrate,
When the data indicating the end of the frame is recognized by the serial channel, there is no need to provide a signal line for notifying the recognition to the direct memory access controller with a chain function, and the frame switching process is executed by interruption to the central processing unit. You may make it.

Further, the chain function provided in the direct memory access controller is not limited to the format described in the above embodiment, and a large number of buffer areas are prepared, and they can be identified one after another by a data storage area such as a descriptor that functions as a pointer. Various formats can be adopted that allow data to be stored for each group by linking.

In the above description, the invention made mainly by the inventor is provided with a communication function having a serial channel and a direct memory access function which supports transfer control of serial data by a high level data link control system which is a use field which is a background of the invention. Although the description has been given of the case where the present invention is applied to a single-chip microcomputer, the present invention is not limited to this. The present invention is generally applied to a data processing device capable of storing a group of data such as a frame in a buffer memory so that a partition can be recognized. Can be. The present invention has at least a serial channel that supports a control procedure for information exchange and the like, and a direct memory access controller with a chain function that directly controls the transfer of information to be exchanged between the memory and the serial channel. It can be applied to those that support the communication function.

〔The invention's effect〕

The following is a brief description of the effects obtained by the representative inventions out of the inventions disclosed in the present application.

That is, according to the first aspect, when data is transferred from the serial channel to the memory so that the delimiter of each frame can be recognized, the frame switching processing such as the change of the data storage address is performed by the data supplied from the signal line. , The processing time can be remarkably reduced without requiring the intervention of a central processing unit.

According to the second invention, it is sufficient that the serial channel and the direct memory access controller mutually arbitrate the internal bus in the same chip, so that a group of data to be exchanged can be recognized in a group. In addition, the speed of the process of storing data in the memory by the direct access control method can be increased, and the versatility of the communication protocol can be obtained by the general-purpose central processing unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer which is an embodiment of a data processing apparatus according to the present invention, and FIG. 2 is an explanatory diagram showing a detailed example of a chain function of a direct access controller. MCU ... microcomputer, CPU ... central processing unit,
DMAC: Direct memory access controller, SIC
…… Serial channel, DM …… Memory, CL …… Signal line,
DD ₁ or DDn ...... descriptor, BA ₁ or BAn ...... buffer area.

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Kenji Miyazaki 2326 Imai, Ome City, Hitachi, Ltd.Device Development Center (72) Inventor Toshio Okochi 2326 Imai, Ome City, Device Development Center, Hitachi, Ltd. 56) References JP-A-59-62938 (JP, A) FACOM 230-75 Hardware Description I, published 48.11, 111-P.145

Claims (3)

(57) [Claims] A memory, a central processing unit, a direct memory access controller, and a serial channel interconnected by a bus, wherein the direct memory access controller communicates with the memory and the serial channel via the bus. The serial channel is a serial interface controller for transmitting information bit-serial with an external device, and the information transmission between the serial channel and the external device. Is a data processing device which enables communication of a transfer data method including an end flag indicating the end of the frame as a group of information, wherein the frame is a data unit of the frame. And a plurality of storage destination areas for storing A signal line is provided separately from the bus between the direct memory access controller and the direct memory access controller. When the serial channel recognizes the end flag indicating the end of the frame of the bit serial information transmission, the signal line is connected to the signal line. The serial channel notifies the direct memory access controller of the recognition via the bus, and in response to the notification, the direct memory access controller transfers and stores a group of information from the serial channel to the memory via the bus. A data processing device for performing a storage switching process of the plurality of storage destination areas of the memory when performing the processing. 2. A plurality of one-to-one descriptors corresponding to each of the plurality of storage destination areas of the memory are set in the memory, and each of the plurality of descriptors is a storage destination corresponding to the descriptor. A first pointer in which the head address of the area is described, a second pointer in which the head address of the storage area specified by the descriptor following the descriptor is described, and a storage destination specified by the descriptor An instruction column in which delimiter information indicating whether or not data transfer of the area has been completed is described, and the direct memory access controller uses the delimiter information in the instruction column of the plurality of descriptors to The data processing apparatus according to claim 1, wherein storage switching processing of the plurality of storage destination areas is performed. 3. The data processing device according to claim 1, wherein said information transmission is performed by a high-level data link control system.