JP2723970B2 - Data transfer control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device which supports DMA (Direct Memory Access) transfer control of data, and a technique for changing and controlling a DMA transfer address. The present invention relates to a technology effective when applied to DMA transfer control of communication data by exchange.

(Prior art)

When performing data transfer between memory and input / output circuits,
To reduce the burden on the microprocessor and improve data transfer efficiency, a DMA controller can be used. This DMA controller performs data transfer control on behalf of the processor. To configure a data transfer channel, a transfer destination address, a transfer source address,
It has a register set for specifying the number of words to be transferred, an enable bit for a transfer operation, and a data transfer mode or a transfer operation mode between memories or between a memory and an input / output circuit. The data is initially set in this register set by the processor.After the initialization, the microprocessor writes the enable bit of the data transfer operation to the status register of the DMA controller. The data transfer control is started in response to a data transfer request from an input / output circuit or the like.

When such a DMA controller is applied to, for example, a communication control device that exchanges data in a packet exchange format, the upper processor initially sets a transfer source address and a transfer destination address to the DMA controller, and the DMA controller performs the initial setting. The transfer of received data is merely controlled according to the set conditions and operation modes.

An example of a document describing DMA transfer control of transmission / reception data in a communication control device is Nikkei Data Pro Microcomputer / Product Report MC68605 (published by Nikkei McGraw-Hill Corporation in 1986).

[Problems to be solved by the invention]

By the way, some data to be transferred includes information indicating the transfer destination and the transfer source in the data itself. For example, a packet logical channel number included in data to be exchanged. The packet logical channel number is a unique number corresponding to a task for processing the data. Therefore, in the data processing by the host processor, the data received by the packet exchange must be transferred to the memory area allocated to the task in accordance with the unique packet logical channel number. However, the conventional DMA controller does not have a function of changing the transfer destination address and the transfer source address according to the information included in the data to be transferred.
When the DMA controller is applied to a communication control device that exchanges data in, for example, a packet exchange format, the DMA controller simply transfers received data to a buffer memory according to an initial setting by an upper processor. For this reason, the upper processor must recognize the packet logical channel number included in the data transferred to the buffer memory and control the retransmission of the received data to another memory area corresponding to the packet logical channel accordingly. However, a burden is placed on the host processor, and the system throughput is reduced.

An object of the present invention is to provide a data transfer control device capable of performing data transfer control for storing data for which a storage area is determined in the area without placing a burden on a host processor. Here, the upper processor means a processor capable of initializing at least the data transfer control device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, using a search table, the type of data to be transferred is determined, the address information corresponding to the determination result is searched, and the data transfer destination address or the data transfer source address is changed based on the searched address information. According to the changed address, data can be DMA-transfer-controlled.

In order to speed up the processing using the search table, information indicating the type of data is input as an address,
It is desirable to configure the search table in an associative memory format that outputs corresponding address information.

Further, in order to freely set the word length of the information indicating the type of data, the search table is divided into a first table in which information indicating the type of data is stored in order, and a data stored in the first table. And the second table storing the address information corresponding to the order of the information held in the first table, and the first table is accessed in order to determine the coincidence with the type of data to be transferred. After that, the address information corresponding to the matched information can be read from the second table.

(Operation)

According to the above-mentioned means, when the storage area of the data is determined in the system operation such as the data to be packet-switched, the type of the data to be transferred according to the predetermined information such as the packet logical channel number And changes the data transfer destination address or the transfer source address based on the recognition result without intervening the control of the upper processor, whereby the unique area assigned to the data to be transferred can be obtained. Data transfer can be performed without imposing a burden on a host processor.

〔Example〕

FIG. 2 shows a configuration example of a communication control system using a DMA controller according to one embodiment of the present invention. The communication control system shown in the figure can be configured as a single chip microcomputer formed on one semiconductor substrate or a communication control board formed on one wiring substrate.

The communication control system shown in FIG. 2 includes an upper processor 2, which controls the entire system, a memory 3, a DMA controller 4, a serial communication interface controller (hereinafter, also simply referred to as an SCI controller) 5, and the like. Although they are not, they share bus 6. The SCI controller 5 includes, but is not limited to, a line control unit for supporting packet exchange according to an HDLC (High Level Data Link Control) procedure, and the protocol control is performed by the host processor 2. ing. DMA controller 4
Transfer data received by the SCI controller 5 to a predetermined area of the memory 3 or transfer data to be transmitted to the memory 3
Transfer control from the predetermined area to the SCI controller 5. The SCI controller 5 asserts a DMA request signal DREQ when requesting the DMA controller 4 to perform data transfer control.
Assert the MA acknowledge signal DACK to the SCI controller 5. The upper processor 2 and the DMA controller 4 are both bus masters, and arbitration of the bus right between them is not particularly limited, but is performed by the upper processor 2. When the DMA controller 4 requests a bus right, the DMA controller 4
BREQ is asserted, and in response to this, the upper processor 2 asserts the bus acknowledge signal BACK to the DMA controller 4, whereby the DMA controller 4 acquires the bus right.

FIG. 1 shows a detailed example of the DMA controller 4.

The DMA controller 4 has a transfer data register 10, a transfer source address register 11, a transfer destination address register 12, and a byte count register 13 as a data transfer channel configuration register set for DMA transfer control. Are connected to the internal buses UB, VB and WB. The transfer data register 10 receives data to be transferred read from the transfer source in accordance with the dual addressing mode. The transfer source address is set in the transfer source address register 11, the transfer destination address is set in the transfer destination address register 12, and the byte count register is set.
13 sets the number of words to be transferred. When the data transfer is started, for example, each time one word of data is transferred, the source address and the destination address are incremented or decremented according to the data transfer mode, and the number of words to be transferred is decremented. Such an increment / decrement is performed by the arithmetic and logic unit 14. The internal buses UB, VB, and WB have control registers 15 in which various control information for designating a data transfer control mode and the like are set by the host processor 2 and the like, and a status for indicating the internal state of the DMA controller 4. A register 16 is coupled to the external bus 6, and an address buffer register 17 for exchanging addresses with the external bus 6 and a data buffer register 18 for exchanging data with the upper bus 6 are provided. I have. Selection of various registers and read / write control, upper processor 2 and SC
The control unit 19 performs exchange of a handshake signal with the I controller 5 and other operation control inside the DMA controller 4.

The host processor 2 performs various initial settings for data transfer control by the DMA controller 4, for example, initial settings for the transfer source address register 11, the transfer destination address register 12, and the like. In particular, the DMA controller 4 of this embodiment
When the data transfer control is started in accordance with the initial setting by the upper processor 2, a function to fetch the data to be transferred, determine the type of the data, and change the source address or the destination address by itself according to the determination result. This DMA
According to the present embodiment, the transfer address is changed according to the packet logical channel number included in the data to be packet-switched.

Here, the format of the data to be packet-exchanged is not particularly limited, but is in a form conforming to the HDLC format, and as shown in FIG. 4, a flag F, an address field A, a control field C, an information field I, a frame check sequence FCS, and a flag F. The information field I contains a packet logical channel number and data. The packet logical channel number is a unique number corresponding to the task for processing the data paired with the packet logical channel number. Therefore, in order for the upper processor 2 to process the received data, the data received by the packet switching is:
According to its unique packet logical channel number, it must be temporarily stored in the memory area allocated to the corresponding task.

The DMA controller 4 has a search table 20 having an associative memory structure so that the DMA transfer address can be changed to a predetermined memory area according to the packet logical channel number. The search table 20 uses the packet logical channel number as a key to search for the start address of the memory area corresponding to the key. When the packet logical channel number is input as an address, the corresponding start address is displayed. Is output. For example, as shown in FIG. 5, the memory 3 corresponds to the packet logical channel numbers 1 to i.
Are set in each of the memory areas ME1 to MEi.
The start addresses of _{1 to} MEi are Ame _{1 to} Amei. At this time,
Given the logical channel number 1 of the search table 20,
Top Ame ₁ of the memory area ME1 corresponding thereto is read.

Since the information supplied to the search table 20 of the received data may be only the packet logical channel number, the information for indicating which byte of the received data of one frame is to be supplied to the search table 20 is: For example, it is initially set in the control register 15. The number of bytes set in this way is decremented every time one byte of data is transferred, and when cleared to 0, the operation of the search table 20 is started.

The search table 20 notifies the control unit 19 by the control signal φ when outputting the head address that matches the packet logical channel number. Thereby, the control unit 19 selects the transfer destination address register 12 or the transfer source address register 11 according to the data transfer mode at that time. For example, when the transfer mode of the received data is designated, the transfer destination address register 12 is selected, and the contents of the transfer destination address register 12 are rewritten and controlled by the head address read from the search table 20. Then, based on the rewritten top address,
The received data is sequentially DMA-transferred to the corresponding memory area.

Next, the data received by the SCI controller 5 is stored in the memory 3
The operation will be described by taking as an example a process of performing a DMA transfer to a predetermined area.

First, the upper processor 2 initializes the DMA controller 4 to perform DMA transfer of the received data. For example, SCI
Information specifying a data transfer mode from the controller 5 to the memory 3 is set in the control register 15, and a transfer destination address register 12 is set with a head address of a predetermined buffer area on the memory 3. After that, an enable bit for enabling the DMA transfer operation is written to the control register 15. When detecting the enable bit, the control unit 19 monitors the DMA request signal DREQ, and starts the DMA transfer control in response to the assertion thereof. When the DMA transfer is started, the first content of the information field I included in the frame received by the SCI controller 5, that is, the packet logical channel number is read into the transfer data register 10 via the data buffer register 18 and read. The packet logical channel number is supplied to an address input terminal of the search table 20 through a predetermined internal bus. The search table 20 searches the head address of the memory area corresponding to the given packet logical channel number using the given packet logical channel number as a key, and if there is a corresponding one, outputs the head address to a predetermined internal bus. Control signal φ is asserted. For example, if the packet logical channel number at that time is 1, the start address Ame of the memory area ME1
₁ is read. When the control unit 19 detects the asserted state of the control signal φ, the control unit 19 selects the transfer destination address register 12 according to the data transfer mode at that time,
Start address Ame ₁ read from search table 20
Rewrites the contents of the transfer destination address register 12. Thereafter, the memory area for the packet logical channels 1 specified by the head address Ame ₁ rewritten ME
The first byte of the data included in the information field I is transferred to 1. Next, the content of the transfer destination address register 12 is incremented to the next address, the value of the byte count register 13 is decremented by one, and the data of the second byte is transferred to the memory area ME1. Data transfer is performed in order until the value of 0 becomes zero. Thus, the transfer of the data corresponding to the logical channel number 1 to the memory area ME1 assigned to the logical channel number is completed.

FIG. 3 shows an embodiment in which a search table is configured in the memory 3 instead of the search table 20 having the associative memory structure. In this case, the search table 30 stores, in order, a channel number table 31 in which packet logical channel numbers 1 to i are stored in order and head addresses Ame _{1 to} Amei of memory areas ME1 to MEi allocated to the packet logical channel numbers. And the start address table 32 described above. When the search table 30 having such a structure is adopted, DMA
The controller 4 ′ includes a start address register 33 for storing the start address At ₃₁ of the channel number table 31, a start address register 34 for storing the start address At ₃₂ of the start address table 32, and a table length of the channel number table 31. Is provided with a table length register 35 that holds a value indicating the number of packet logical channel numbers stored in the. In addition, the DMA controller 4 'is not shown in FIG.
Various registers and control units similar to those in the figure are included.

In the system configuration shown in FIG. 3, when the data received by the SCI controller 5 in the packet switching format is DMA-transferred to a predetermined area of the memory 3, the upper-level processor performs DMA transfer of the received data in the same manner as described above. Initialize the controller 4 '. For example, SCI controller 5
The information for designating the data transfer mode from the memory 3 to the memory 3 is set, and the start address of a predetermined buffer area on the memory 3 is set as the transfer destination address. Thereafter, an enable bit for enabling the DMA transfer operation is written to the DMA controller 4 '. When detecting the enable bit, the DMA controller 4 'monitors the DMA request signal DREQ, and starts the DMA transfer control in response to the assertion thereof. When the DMA transfer is started, the first content of the information field I included in the frame received by the SCI controller 5, that is, the packet logical channel number is read into the data buffer register. When a packet logical channel number is read, DMA controller 4 'reads the first packet logical channel number 1 channel number table 31 by using the head address At ₃₁ held in the start address register 33 is held This is compared with the logical channel number held by the transfer data register. When the comparison result is inconsistent, the values of both the start address registers 33 and 34 are incremented by 1 and the value of the table length register 35 is decremented by 1, and the same operation is repeated thereafter. For example, if the packet logical channel number included in the received data is i, the packet logical channel number i
Can be obtained. When the packet logical channel number i obtained from the channel number table 31 matches the packet logical channel number held in the transfer data register, the control unit is notified of that fact. At this time, the start address At ₃₂ initially set in the start address register 34, that is, the start address of the start address table 32 is the start address At
It is incremented by the same number of times as ₃₁ , ie, i times.
As a result, the DMA controller 4 'reads the corresponding start address Amei from the start address table 32 using the value of the start address register 34. Then, the control unit selects the transfer destination address register 12 according to the data transfer mode at that time, and rewrites the contents of the transfer destination address register 12 with the start address Amei read from the start address table 32. Thereafter, the first byte of the data included in the information field I is transferred to the memory area MEi for the packet logical channel number i specified by the rewritten head address Amei. Next, the contents of the transfer destination address register 12 are incremented to the next address, the value of the byte count register 13 is decremented by one, and the data of the second byte is transferred to the memory area Mei. Data transfer is performed in order until the value of 13 becomes 0. In this way, the transfer of the data corresponding to the logical channel number i is completed to the memory area MEi assigned to the logical channel number i.

According to the above embodiment, the following effects can be obtained.

(1) When the storage area of the data is predetermined according to the packet logical channel number in the data processing by the host processor 2 such as the data to be exchanged, the type of the data to be transferred is included in the data. Recognition is performed based on the packet logical channel number, and the DMA controller 4, 4 'itself changes the data transfer destination address according to the recognition result. Therefore, data transfer to a unique memory area assigned in accordance with the packet logical channel number can be performed without placing a burden on the host processor.

(2) Due to the above operation and effect, the upper processor 2 needs to control the retransmission of the data once DMA-transferred to the buffer memory to the area corresponding to the packet logical channel again irrespective of the packet logical channel number. As a result, the throughput of the system can be improved.

(3) The address information to be changed can be obtained by one memory access by using the search table 20 having the associative memory structure. Therefore, the type of data to be transferred can be recognized and the address information corresponding to the type can be obtained at high speed. Moreover, the search table 20
The search processing speed is further improved by embedding the in the DMA controller.

(4) A channel number table 31 for recognizing a packet logical channel number of data to be transferred and a head 32 holding a head address of a memory area allocated to each packet logical channel number in the order of the packet logical channel number. When the search table 30 is configured separately, the word length of the packet logical channel number can be set freely. Moreover, by configuring the search table 30 in the external memory 3, the DMA controller 4 '
The amount of internal hardware can be reduced. However, since the search table 30 must be searched every time in order from the beginning, the search processing speed is reduced. To improve the search processing speed to some extent, it is necessary to consider, for example, providing a buffer RAM (random access memory) on the data output side of the DMA controller 4 '.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.

For example, the search table 20 is arranged outside the DMA controller 4, or the search table 30 is stored in the DMA controller 4 '.
It may be built in. Further, the information indicating the type of data to be transferred is not limited to the packet logical channel number, and has a property appropriately determined according to the system configuration to which the present invention is applied. In the above embodiment, the DMA of the received data is
The case where the transfer destination address is changed by the DMA controller itself has been described by taking transfer as an example. However, the present invention is not limited to this, and can be applied to the case where the transfer source address is changed.

In the above description, the case where the invention made by the inventor is mainly applied to a single-chip microcomputer or a communication control board used in a communication control system which is a utilization field as a background has been described.
The present invention is not limited to this, and can be widely applied to the DMA controller itself and the like. INDUSTRIAL APPLICABILITY The present invention can be applied to a condition for DMA-transferring data in which a unique storage area is determined at least according to the type of data.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, when performing a DMA transfer of data whose unique storage area is determined according to the type of data, the data to be transferred is determined based on predetermined information such as a packet logical channel number included in the data to be transferred. Since the data transfer control device itself changes the data transfer destination address according to the recognition result, the upper processor is burdened with transferring data to a unique area previously allocated to the data to be transferred. There is an effect that it can be performed without.

With the above effects, it is possible to improve the throughput of a system capable of controlling the DMA transfer of data.

In addition, information indicating the type of data is input as an address, and a search table having an associative memory structure that outputs address information corresponding to the address is adopted, so that information on a transfer destination or transfer source to be changed can be obtained at high speed. be able to.

Then, a first table storing information indicating the type of data in order and a second table holding address information corresponding to the information stored in the first table in accordance with the order of the held information of the first table. , The word length of the information indicating the type of data can be set freely.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a detailed example of a DMA controller according to an embodiment of the present invention. FIG. 2 is a block diagram showing a part of a communication control system to which the DMA controller of FIG. 1 is applied. FIG. 4 is a block diagram showing another communication control system according to another embodiment of the present invention. FIG. 4 is a format diagram showing an example of an HDLC format of data to be packet-switched. FIG. FIG. 3 is an explanatory diagram of a memory space showing a relationship with a memory area. 2 ... upper processor, 3 ... memory, 4 ... DMA controller, 4 '... DMA controller, 5 ... SCI controller, 10 ... transfer data register, 11 ... transfer source address register, 12 ... transfer destination Address register, 13 ...
Byte count register, 15 Control register, 19 Control unit, 20 Search table, ME1 to MEi
Memory area, Ame _{1 to} Amei ...... head address, 30 ... search table, 31 ... channel number table, 32 ... head address table, 33, 34 ... head address register, 35
.... Table length register.

Claims (5)

(57) [Claims] 1. A data transfer control device which includes a register set and a control unit for DMA transfer control, and transfers a series of data exchanged in a packet of plural words including a packet logical channel number and other information. The position of the packet logical channel number in the data is indicated by a set value of a control register in the register set, and the type of the data is determined based on the packet logical channel number. Searches the address information using a search table that associates the type of data with the address information, changes the data transfer destination address or the data transfer source address according to the searched address information, and DMA-transfers the data according to the changed address. A data transfer control device configured to be controllable. 2. The search table according to claim 1, wherein the search table is configured in an associative memory format in which a packet logical channel number is input as an address and corresponding address information is output. Data transfer control device. 3. The search table stores a first table in which packet logical channel numbers are stored in order and address information corresponding to data stored in the first table in correspondence with the order of information held in the first table. And the second table is accessed in order from the first table,
2. The data transfer control device according to claim 1, wherein, after a match with the packet logical channel number is determined, address information corresponding to the matched information is read from the second table. . 4. A microcomputer wherein the data transfer control device according to claim 1 is formed on one semiconductor substrate. 5. The microcomputer according to claim 4, wherein said microcomputer further comprises a processor and a memory.