JP3270149B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device suitable for use in, for example, a computer system.

[0002]

2. Description of the Related Art As a data transfer method in a conventional computer system, for example, a DMA (Direct Memory) is used.
Access) is known.

That is, in the DMA system, for example, a main memory (main storage device) of a computer system is
When transferring data to a device such as an image processing board or an audio processing board connected to the DMA controller, a DMA controller performs control necessary for reading and writing data (for example, read and write) in place of a CPU (Central Processing Unit) of a computer system. A signal or a write signal is output to the main memory and the device), and data is directly transferred from the main memory to the device without going through the CPU.

Therefore, according to this DMA system, the CPU
Has little to do with the data transfer process,
The CPU can perform other processing, and can improve the processing capability of the device.

[0005]

By the way, when data is transferred by DMA, for example, the start address (start address) and data length of the data to be transferred, the data transfer destination address (device address), etc. It is necessary to set (notify) transfer specification information as information necessary for transfer to the DMA controller, and this is performed by the CPU.

Therefore, for example, if there is a change in the data to be transferred, its data length, the address of the data transfer destination, etc.,
Each time, the CPU sets all of the transfer specification information to the DMA controller.

Therefore, there has been a problem that the time required for the CPU to transfer data increases and the processing performance of the apparatus decreases.

The present invention has been made in view of such a situation, and further improves the processing capability of the apparatus.

[0009]

A data transfer apparatus according to the present invention, which meets the above-mentioned problems, can be implemented without using a central processing unit.
A data transfer device that controls data transfer between different devices connected to a main bus, and reads out transfer data number information and transfer destination information stored in a memory in a data transfer source device in association with transfer target data. In addition, the transfer target data is transferred to a data transfer destination device according to the transfer data number information and the transfer destination information.

[0010] Another data transfer apparatus of the present invention corresponding to the above problem is a data transfer apparatus for controlling data transfer between a main memory and a device without passing through a central processing unit. A control register for temporarily storing the number of transfer data and a transfer destination address read from a memory incorporated in the device, a data number latch circuit for latching the transfer data number, and an address latch circuit for latching the transfer destination address; A control circuit for controlling reading of data from the main memory or the device, or writing of data to the main memory or the device, wherein the control circuit controls the number of transfer data in the main memory or the memory incorporated in the device. The transfer data continuously stored at the transfer destination address Wherein the transferring of data to the destination address.

[0011] Another data transfer apparatus of the present invention corresponding to the above problem is a data transfer apparatus for controlling data transfer between a main memory and a device without passing through a central processing unit. A control register for temporarily storing a transfer data number and a transfer destination address read from a memory incorporated in the device, a data number latch circuit for latching the transfer data number, and a first address latch for latching the transfer destination address A circuit, a second address latch circuit that latches a transfer source address, and a control circuit that controls reading of data from the main memory or the device or writing of data to them, and the control circuit includes: Based on the transfer source address, a memo stored in the main memory or the device. And reading the transfer data number and the transfer destination address from the memory device and transferring the data of the transfer data number stored continuously to the transfer data number and the transfer destination address to the transfer destination address. I do.

[0012]

[0013]

[0014]

In the data transfer apparatus of the present invention, the transfer data number information and the transfer destination information (for example, the transfer destination address) stored in the memory of the data transfer source apparatus (for example, main memory) in association with the transfer target data. ) Is read, and the transfer target data is transferred to a data transfer destination device (eg, device) according to the transfer data number information and the transfer destination information. Therefore, it is not necessary for the central processing unit to set the transfer data number and the transfer destination address every time the data is transferred, so that the processing performance of the device can be improved.

Further, since the transfer data number information and the transfer destination information (eg, transfer destination address) are often unique to the data to be transferred, they are stored in association with each other (eg, on a memory). To be stored continuously)
Thereby, the transfer efficiency of the entire data by the data transfer device of the present invention can be improved.

[0016]

FIG. 1 is a block diagram showing the configuration of an embodiment of a computer system to which a data transfer device according to the present invention is applied. The CPU 1 controls the entire device (system), reads a system program, a user program, and the like stored in the main memory 2 and operates according to the read program. The main memory 2 stores data necessary for the operation of the apparatus, in addition to a system program and a user program. The DMA controller 3 is configured, for example, as shown in FIG.
The transfer of data from (device 5) to device 5 (main memory) is controlled.

That is, the control circuit 11 controls each block constituting the DMA controller 3 and also controls the device 5
A DMA request (DMA request) from (FIG. 1) is received (DMA request signal is received), and if the computer system (FIG. 1) can transfer data by DMA, the DMA request is received. Is granted (outputs a permission signal).

Further, when there is a request for DMA, the control circuit 11 issues a bus request to the CPU 1 (FIG. 1) (outputs a bus request signal). Then, when the address bus, the data bus, and the control bus (hereinafter, collectively referred to as a main bus) are free (when they are unused), the CPU 1 causes the signal (permission signal) indicating that the main bus is free. Is output, the control circuit 11 receives this.

When the control circuit 11 receives a permission signal for the bus request signal from the CPU 1, the control circuit 11
Instead of 1, a control signal such as a read signal or a write signal for reading or writing data is output to the control bus. Further, the control circuit 11
When the data transfer by A is completed, an interrupt request is issued to CPU 1 (an interrupt signal is output) to notify that the data transfer has been completed.

The control register 12 includes, for example, a CP
DMA controller 3 from U1 or the like via a data bus
, Or transfer specification information read from, for example, the main memory 2 or a memory (not shown) incorporated in the device 5 and necessary as data when transferring data. The timing control circuit 13 supplies a clock to each block constituting the DMA controller 3 according to the instruction held in the control register 12, and controls the operation timing.

The data number latch circuit 14 latches the number of data to be transferred (the number of data) in the transfer specification information. The down counter 15 reads the number of data latched in the data number latch circuit 14 at the start of data transfer, and decrements the value by one each time one data is transferred. That is, the down counter 15 counts the remaining number of data to be transferred.

The address latch circuit 16 is provided with an address of a built-in memory of the transfer destination device (in FIG. 1, one of the main memory 2 and the device 5 in FIG. 1) (data of the transfer specification information). An address of a transfer destination device (for example, the highest address or the lowest address of a data transfer area provided in advance in the memory) (hereinafter referred to as a transfer destination address) is latched. The address counter 17 reads the transfer destination address latched by the address latch circuit 16 at the start of data transfer, and increments or decrements the value each time one data is transferred.

The address counter 17 performs the above operation only when, for example, 1 is set in the flag register 18 from 0 and 1 indicating that the increment or decrement of the stored value is permitted. When 0 or 1, for example, is set in the flag register 18 to indicate that the increment or decrement of the stored value is prohibited in the flag register 18, the stored value is held as it is.

The flag register 18 stores a command or transfer specification information supplied through the timing control circuit 13 and held in the control register 12 according to
Set to either 0 or 1.

In the flag register 19, according to an instruction or transfer specification information supplied through the timing control circuit 13 and held in the control register 12,
For example, one of 0 and 1 indicating that increment or decrement of the stored value of the address counter 21 is permitted, or 0 and 1 indicating that increment or decrement of the stored value is prohibited.
For example, 0 is set.

A flag (0 or 1) can be set in the flag register 18 or 19 at the timing of the clock output from the timing control circuit 13, respectively.

The address latch circuit 20 is provided, for example, in advance in an address of a memory incorporated in a transfer source device (in FIG. 1, either the main memory 2 or the device 5) for transferring data, for example, in the memory. The uppermost address, the lowermost address, and the like of the data transfer area (hereinafter, referred to as a transfer source address) are latched. The address counter 21 reads and stores the transfer source address latched in the address latch circuit 20 at the start of data transfer, and increments or decrements the stored value every time one data is transferred.

The address counter 21 performs the above operation only when 1 is stored in the flag register 19 (when increment or decrement of the storage value of the address counter 21 is permitted). Is stored in the address counter 21 (when increment or decrement of the storage value of the address counter 21 is prohibited), the stored value is held as it is.

The data latch circuit 22 temporarily latches data input to the DMA controller 3 via the data bus.

The selector 4 (FIG. 1) decodes the address on the address bus, and outputs a selection signal to the device 5 when it decodes the address. The device 5 is a so-called peripheral device in a computer system, such as an image processing board or a sound processing board.

Next, the operation will be described. For example, the data stored in the data transfer area of the main memory 2 is transferred to the data transfer area of the internal memory of the device 5 by the DM.
When the transfer is performed by A, the data transfer area of the internal memory of the device 5 to which the data is to be transferred, for example, as the transfer specification information of the data, is associated with the data to be transferred on the data transfer area of the main memory 2 The head address (transfer destination address), the number of data to be transferred, and the like are stored.

That is, data to be transferred and transfer specification information of the data are stored on the data transfer area of the main memory 2.
For example, they are continuously stored as shown in the memory map of FIG. This transfer specification information is stored in, for example, the main memory 2
CPU1 computes and stores data when writing data to
Let

That is, in the data transfer area of the main memory 2, the data to be transferred and the transfer specification information are sequentially transferred from the highest address P to the transfer specification information S1 for the data group D1, the data group D1, and the data group D2. The transfer specification information S2, the data group D2, the transfer specification information S3 for the data group D3, and so on are stored in advance.

Further, the CPU 1 (FIG. 1)
The source address is set in the address latch circuit 20 of the controller 3 (FIG. 2). That is, in the CPU 1, the head address (transfer source address) P (FIG. 3) of the data transfer area of the main memory 2 in which the transfer specification information is stored together with the data to be transferred is output to the data bus, and this is the address of the DMA controller 3. Latch circuit 20
(FIG. 2).

When the device 5 (FIG. 1) requests data transfer by DMA, that is,
When the request signal is output on the control bus,
It is received by the control circuit 11 of the DMA controller 3 (FIG. 2). Then, a bus request signal is output from the control circuit 11 to the CPU 1 via the control bus, and thereafter, when the main bus is vacant (unused), the CPU 1 outputs a permission signal indicating that the main bus is vacant. Then, it is received by the control circuit 11. Control circuit 11
When the permission signal from the CPU 1 is received, that is, when it is determined that the main bus is free, the device 5
A permission signal indicating that data transfer by A is permitted is output, and DMA transfer from the main memory 2 to the device 5 is performed.
Starts data transfer.

That is, the transfer source address P latched by the address latch circuit 20 is read out by the address counter 21 and set there. Then, the transfer source address P set in the address counter 21 is output onto the address bus at the timing when the timing control circuit 13 outputs the clock.

Then, from the address indicated by the transfer source address P on the address bus, ie, the start address P of the data transfer area of the main memory 2, the transfer destination address A1 of the transfer specification information S1 stored therein (FIG. 3) Is read out and output on the data bus. The transfer destination address A1 on the data bus is supplied to the address latch circuit 16 (FIG. 2) and latched.

Further, when the next clock is output from the timing control circuit 13, the stored value of the address counter 21, that is, the transfer destination address P is incremented by 1, for example, to P + 1, which is output on the address bus. . Then, the address P + in the main memory 2
1, the data number L1 of the transfer specification information S1 (data group D
1 (FIG. 3) is read out and output on the data bus. The number of data L1 on the data bus is
The data is supplied to the data number latch circuit 14 and latched.

Here, it is assumed that the clock is sequentially output from the timing control circuit 13 as described above, and each block operates at the timing.

In the flag registers 18 and 19, for example, 1 is set, so that the stored values in the address counters 17 and 21 are sequentially incremented, for example.

The data number L1 latched by the data number latch circuit 14 is read out therefrom, and the town counter 1 is read.
Set to 5. At the same time, the transfer destination address A1 latched by the address latch circuit 16 is read therefrom, set in the address counter 17, and the address counter 21 is incremented by one, so that the stored value becomes P + 2.

The stored value of the address counter 21, ie, the address P + 2, is output on the address bus, and the data of the data group D1 (FIG. ) Is read out and output on the data bus. Data on the data bus is supplied to the data latch circuit 22 and latched.

Then, the data latched by the data latch circuit 22 is stored in the address indicated by the transfer destination address A1 set in the address counter 17, that is, in the data transfer area of the internal memory of the device 5 to which the data is transferred. Transferred via data bus.

As described above, the data stored at the address P + 2 of the main memory 2 is transferred to the address A1 of the memory incorporated in the device 5.

When the transfer of the data latched by the data latch circuit 22 is completed, the number L1 of data to be transferred, which is stored in the down counter, is decremented by one to L1-1.

At the same time, when the address A1 stored in the address counter 17 on the memory incorporated in the device 5 is 1
The address P + 2 on the main memory 2 stored in the address counter 18 is incremented by 1 to P + 3.

Then, the stored value of the address counter 21,
That is, the address P + 3 is output on the address bus, and the address indicated by the address P + 3, that is, the main memory 2
From the address P + 3 of the data transfer area of the data group D1
(FIG. 3) is read out and output on the data bus. The data on the data bus is
And latched.

Further, the data latched by the data latch circuit 22 is stored in the address indicated by the transfer destination address A1 + 1 set in the address counter 17, that is, in the data transfer area of the internal memory of the device 5 to which the data is transferred. Transferred via data bus.

As described above, the data stored at the address P + 3 of the main memory 2 is transferred to the address A1 + 1 of the internal memory of the device 5.

When the transfer of the data latched in the data latch circuit 22 is completed, the number L1-1 of data to be transferred, which is stored in the down counter 15, is decremented by one to L1-2.

Thereafter, the same operation is repeated until the value stored in the down counter 15 for counting the number of remaining data of the data group D1, that is, the remaining number of data to be transferred becomes zero.
L1 data of the data group D1 stored in the main memory 2 is transferred to the device 5.

When the stored value of the down counter 15 becomes 0, that is, when the transfer of the data of the data group D1 is completed, an interrupt signal is output from the control circuit 11 to the CPU 1 to notify that the data transfer has been completed. .

As described above, the data and the transfer specification information are stored in association with each other, for example, the data and the transfer specification information are continuously stored in the main memory 2, and the same as the case of reading the data. Since the transfer specification information is read by the operation, every time data is transferred,
It is not necessary for the CPU 1 to set all the transfer specification information, so that the processing capability of the device can be improved.

Further, when the data structure to be transferred is as shown in FIG. 3, for example, only the address of the transfer specification information of the data to be transferred first (for example, address P in FIG. 3) is used by the CPU 1. Is given to the DMA controller 3 without the CPU 1 being involved.
Since the data is transferred, the efficiency of the CPU 1 and the efficiency of software development can be improved.

The transfer specification information is often unique to the data to be transferred. In this case, as shown in FIG. 3, the data groups and the transfer specification information are arranged continuously. In addition, the transfer efficiency of the entire data can be improved.

In the DMA controller 3,
Setting the address latched by the address latch circuit 20 in the address counter 21 can be prohibited. That is, the address stored in the address counter 21 can be held as it is.

Thus, after the data transfer is completed as described above, the address P + 2 + L1, ie, the top address of the transfer specification information S2 (FIG. 3) on the main memory 2, is stored in the address counter 21. Therefore, next, when the DMA request signal is received by the control circuit 11, this transfer specification information S2 is read out by the DMA controller 3, and based on this, the data transfer is performed as described above. .

Therefore, in this case, data can be transferred quickly.

In this embodiment, every time one data is transferred, the address counter 17 is incremented by one, and the address A1 of the memory built in the device 5 is read.
, The data is sequentially stored. However, the data can be transferred only to the address A1 of the memory incorporated in the device 5 without incrementing the address counter 17.

Further, after the data transfer of one data group such as the data group D 1 is completed, when data is to be transferred next by DMA, the address counter 21 is reset, that is, the data is latched by the address latch circuit 20. It is possible to set the address P present in the address counter 21 and transfer the data of the data group D1 again.

The device 5 as a data transfer destination
Of the internal memory of the control circuit 11
Can specify that address.
In this case, the DMA controller 3 has the address latch circuit 16, the address counter 17, the flag register 1
8 and the selector 4 need not be provided, and the device can be made compact.

Further, the address of the transfer data to be stored in the main memory 2 as the data transfer source can be fixed, and the control circuit 11 can specify the address. In this case, there is no need to provide the address latch circuit 20, the address counter 21, and the flag register 19 in the DMA controller 3, so that the device can be made compact and the speed of data transfer can be increased.

Further, the control circuit 11 can be made to manage the input and output of data of the main memory 2 or the device 5, respectively. In this case, it is not necessary to provide the data latch circuit 22 in the DMA controller 3, and
The device can be made compact.

Further, it is possible to make the control circuit 11 designate the device 5. In this case, there is no need to provide the selector 4 in the device, and the device can be made compact.

In the present embodiment, the transfer specification information is the transfer destination address and the number of data for the sake of simplicity, but the present invention is not limited to this. That is,
The transfer specification information refers to all information (for example, information required depending on the system configuration) required when transferring data, such as a transfer source address and an I / O port address, in addition to a transfer destination address and the number of data. Is different).

Further, in this embodiment, the transfer specification information itself is stored in the main memory 2 together with the data. However, the transfer specification information is stored in another address space, for example. In this case, an address (pointer to the transfer specification information) at which the transfer specification information is stored may be stored as the transfer specification information together with the data.

In this embodiment, the data and the transfer specification information of the data are stored in the address space of the main memory 2 so as to be continuous as shown in FIG. The present invention is not limited to this. For example, a predetermined offset may be provided and stored.

Further, instead of storing all the transfer specification information together with the data in the main memory 2,
Some of them can be stored, and the other can be set by the CPU 1 to the DMA controller 3.

In this embodiment, the data transfer between the main memory 2 and the device 5 has been described for the sake of simplicity. For example, the data transfer between the main memory 2 and another device, Between devices, data transfer can be performed in the main memory 2 in the same manner.

[0070]

As described above, according to the data transfer device of the present invention, the transfer data number information and the transfer data stored in the memory of the data transfer source device (eg, main memory) in association with the transfer target data. Destination information (eg, forwarding address)
And transfers the data to be transferred to a data transfer destination device (eg, device) according to the transfer data number information and the transfer destination information. Therefore, it is not necessary for the central processing unit to set the transfer data number and the transfer destination address every time the data is transferred, so that the processing performance of the device can be improved.

Furthermore, since the transfer data number information and the transfer destination information (eg, transfer destination address) are often unique to the data to be transferred, they are stored in association with each other (eg, on a memory). To be stored continuously)
Thereby, the transfer efficiency of the entire data by the data transfer device of the present invention can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a computer system to which a data transfer device of the present invention is applied.

FIG. 2 is a more detailed block diagram of a DMA controller 3 of the embodiment of FIG.

FIG. 3 is a diagram showing a memory map of a data transfer area provided in a main memory 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main memory 3 DMA controller 4 Selector 5 Device 11 Control circuit 12 Control register 13 Timing control circuit 14 Data number latch circuit 15 Down counter 16 Address latch circuit 17 Address counter 18, 19 Flag register 20 Address latch circuit 21 Address counter 22 Data latch circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13/28

Claims (3)

(57) [Claims] 1. A data transfer device for controlling data transfer between different devices connected to a main bus without passing through a central processing unit, wherein the data transfer device associates a memory in a data transfer source device with data to be transferred. A data transfer device for reading out the transfer data number information and the transfer destination information stored in advance and transferring the transfer target data to the data transfer destination device according to the transfer data number information and the transfer destination information. 2. A data transfer device for controlling data transfer between a main memory and a device without passing through a central processing unit, the transfer data being read from the main memory or a memory incorporated in the device. A control register for temporarily storing a number and a transfer destination address; a data number latch circuit for latching the transfer data number; an address latch circuit for latching the transfer destination address; reading data from the main memory or the device; Or a control circuit for controlling the writing of data to them, wherein the control circuit continuously stores the number of transfer data and the transfer destination address in the main memory or a memory incorporated in the device. Transfer the data of the number of data to the transfer destination address. Data transfer apparatus according to claim. 3. A data transfer device for controlling data transfer between a main memory and a device without passing through a central processing unit, the transfer data being read from the main memory or a memory incorporated in the device. A control register for temporarily storing a transfer number and a transfer destination address; a data number latch circuit for latching the transfer data number; a first address latch circuit for latching the transfer destination address; and a second address latch for latching a transfer source address And a control circuit that controls reading of data from or writing data to the main memory or the device, and wherein the control circuit is configured to control the main memory or the device based on the transfer source address. From the internal memory of the It reads the data transfer apparatus characterized by transferring the transfer data number of the data stored continuously in the transfer data number and the destination address to the destination address.