JP2000330866A - Method and system for controlling memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control system capable of efficiently processing access requests from plural access request devices. SOLUTION: The memory control system is provided with a memory 5 having plural memory banks 51 to 54 capable of independently storing row addresses, plural request devices 2, 6, 7 capable of accessing the memory 5 and a memory controller 4 for receiving access requests from respective request devices 2, 6, 7, selecting any one of the requests by arbitration and allowing the request device outputting the selected access request to access the memory 5. In the case of continuously executing plural accesses, each request device issues a continuous access request indicating the continuous accesses. At the time of permitting the request device issuing the continuous access request to access the memory 5, the memory controller 4 preferentially selects an access request from the request device at the time of succeeding arbitration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method and system for controlling memory access to a main storage device applied to a computer system in which a main storage device and a plurality of components are connected.

[0002]

2. Description of the Related Art A computer system generally includes a plurality of components such as a CPU, a cache memory, an input / output device, and a main storage device. In such a computer system, the main storage device is connected to a plurality of components via a bus or a network, and each component sends a signal indicating that there is an access request to the memory control device, and simultaneously accesses the memory control device. , A target address, the number of access words, and the like, and perform memory access.

Japanese Patent Application Laid-Open No. 9-223066 discloses a synchronous DRA having a plurality of internal banks in a main storage device.
A memory control method using M is disclosed. In this memory control method, a directory is placed in a part of a main storage device configured by a synchronous DRAM, and the memory control device uses a specific address bit to specify a synchronous DR.
By selecting an internal bank of the AM and arranging the memory block and the directory corresponding to the memory block in different internal banks, directory access and data access are performed in a state where each row address is held.

According to the above memory control, when two types of data are successively accessed, the next access can be performed while holding the row address of the previously performed access. The specification of the row address at the time of access to be performed can be omitted, and the access can be speeded up accordingly.

[0005] Incidentally, the memory control device normally accepts access requests from a plurality of components, and when a plurality of components issue an access request at the same time, the access request from any component is determined. It is necessary to decide whether to choose by arbitration. Further, when it is required to continuously process a plurality of accesses from a certain component, it is necessary to control not to accept accesses from other components during the process.
A plurality of such accesses that must be processed continuously are called "atomic accesses".

When an atomic access is required as a memory control for performing an atomic access, a signal indicating that the bus is occupied is sent on the bus, so that another component sends an access request on the bus. There is a way to control not to. In the case of this control method, each component checks whether or not a signal indicating that the bus is occupied is transmitted on the bus, and determines whether to issue an access request.

As an example of a memory control system for performing an atomic access, Japanese Patent Application Laid-Open No. 7-287667 discloses an STO.
A system that performs exclusive control using a P_MOST line and a CLIENT_OP line is disclosed. In this system, first, a device that performs an atomic access is a STOP_MOS
Assert line T. Next, the memory access is performed after the state of the CLIENT_OP line becomes an atomic owner. At this time, the CLIENT_OP line of the device other than the atomic owner is in a state indicating that the atomic access is being performed by another device, and is basically controlled so as not to perform the memory access.

[0008]

However, the above-mentioned conventional memory control has the following problems.

In the method described in Japanese Patent Application Laid-Open No. 9-223066, while two types of data are continuously accessed,
When an access request is issued from another component,
The arbitration determines from which component the access request is processed. If an access request from another component is selected at the time of this arbitration, the stored row address changes, and the row address is set again. It cannot be planned. This problem is more likely to occur as the number of devices that issue access requests increases.

In the device described in Japanese Patent Application Laid-Open No. 7-287667, since each component performs a state check using a control line independently, when switching an access request from each component, Delay increases. In addition, since exclusive control is performed using a dedicated line for atomic access control, processing on the device side that issues an access request becomes complicated.

An object of the present invention is to provide a memory control method and a memory control system capable of solving the above-mentioned problem and efficiently processing access requests from a plurality of access request devices.

Another object of the present invention is to provide a memory control method and a memory control system capable of processing a series of accesses at a high speed without being hindered by an access request from another access request device. is there.

Another object of the present invention is to provide a memory control method and a memory control system which can perform exclusive control efficiently and do not complicate the processing on the access requesting device side. .

It is another object of the present invention to provide a memory control method and a memory control system capable of efficiently switching and processing access requests from a plurality of access request devices.

[0015]

In order to achieve the above object, a memory control method according to the present invention controls access to a memory having a plurality of memory banks each of which can independently hold a row address. Receiving an access request from a plurality of access request devices capable of accessing the memory, selecting one of the access requests by arbitration and permitting access to the memory; It is determined whether or not the access request selected by the arbitration is a continuous access request indicating that a plurality of accesses are to be continuously performed. If the access request is a continuous access request, the access request is determined at the next arbitration. Preferentially selecting an access request from the access request device that issued the request.

In the above method, when the result of the determination as to whether or not the request is a continuous access request is a continuous access request, information indicating the continuous access state and the access requesting device that issued the access request are specified. In other cases, information indicating the normal access state is held, and based on the held information, whether the current access state is the continuous access state, May further include a step of determining whether or not the user is performing continuous access.

In the above method, when the result of the determination as to whether or not the request is a continuous access request is a continuous access request, the step of holding the page address of the request; From an access request device other than the access request device performing
When a normal access request that is different from the held page address and is not a continuous access request is issued, the method may further include the step of accepting the access request and permitting access to the memory.

A memory control system according to the present invention comprises a memory means having a plurality of memory banks, each of which can independently hold a row address; a plurality of access request means capable of accessing the memory means; Memory control means for receiving an access request from a plurality of access request means, selecting one of the access requests by arbitration, and permitting access to the memory means, wherein the plurality of access request means each include: When a plurality of accesses are performed consecutively, the memory control unit is configured to issue a continuous access request to that effect, and the memory control unit permits the access request unit that issued the continuous access request to access the memory unit. In such a case, at the time of the next arbitration, the access request from the access request unit is preferentially selected. Characterized in that it has been.

In the above memory control system, the memory control means arbitrates access requests issued from the plurality of access request means, and the access request selected by the arbitration means is a continuous access request. In some cases, information indicating the continuous access state and information for specifying the access requesting unit that issued the access request are held; otherwise, information indicating the normal access state is held. Flag means for determining whether the memory control means is in a continuous access state based on information held in the flag means. In the case of arbitration, the access request from the access request means that is currently performing continuous access may be preferentially selected.

In the memory control system, each of the plurality of access request means sends a command signal including a continuation instruction bit indicating whether or not to make a plurality of accesses continuously to the memory control means together with the access request. The flag means may be configured to take one of a continuous access state and a normal access state based on the information of the continuous instruction bit.

In the above-mentioned memory control system, the memory control means further comprises a register means for holding a page address of the request when the access request selected by the arbitration means is a continuous access request; However, when the memory control means is in the continuous access state, from the access request means other than the access request means currently performing continuous access, the page address is different from the page address held in the register means, and
When a normal access request that is not a continuous access request is issued, the access request may be accepted and access to the memory unit may be permitted.

(Operation) In the present invention as described above, when a continuous access request for processing a plurality of accesses continuously is selected by arbitration, a series of accesses relating to the continuous access request is processed with priority. Is done. During this process, since an access request from another requesting device is not accepted, an access request from another component is selected and held during continuous access as described above as a conventional problem. It does not occur that the row address changes and the row address is set again.

In the present invention, in which the command signal including the continuous instruction bit is transmitted together with the access request, the continuous access request can be indicated to the memory control means simply by setting the continuous instruction bit.
It is not necessary to perform special control such as checking the state of another access requesting device using a control line as in the related art. Therefore, according to the present invention, the delay in switching the access request from each access request device does not increase, and the processing on the access request device side does not become complicated.

According to the present invention, when a normal access request having a different page address is issued from another access request means during continuous access, interrupt control can be performed for a device that accepts the access request, and other access requests can be controlled. Processing can be performed without waiting for accesses other than the continuous page address of the request unit.

[0025]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the memory control system of the present invention. In this memory control system, N processors 1-1 to 1-N are connected to an inter-processor network 8.
Are parallel computer systems connected to each other via a.
Each of the processors 1-1 to 1-N has the same configuration. FIG. 1 shows only the configuration of the processor 1-1 for convenience.

Each of the processors 1-1 to 1-N comprises a CPU 2, a cache memory 3, a memory control device 4, a memory 5, an input / output device 6, and an inter-processor communication device 7. The CPU 2 controls arithmetic processing and the like, and the input / output device 6 controls input / output processing. The inter-processor communication device 7 transmits and receives data between its own processor and another processor. The inter-processor communication device 7 reads data from the memory 5 in accordance with an instruction from the CPU 2, and reads data from the memory 5.
And writes the data sent from another processor via the inter-processor network 8 to the memory 5.

Each of the CPU 2, the input / output device 6, and the inter-processor communication device 7 (hereinafter collectively referred to as “request devices”) is transmitted to the memory control device 4 and the memory 5 as necessary. It issues an access request (request signal a) and sends out a command signal b. FIG. 2 shows an example of the command signal b sent from each requesting device to the memory control device 4.

The command signal b includes four types of request (request), word length, continuous instruction bit, and address.
Two items are defined. The request type items include “Word Read” and “Word Write”, which indicate that reading and writing are performed in word units by specifying the number of words, and “Block Read”, which indicates that reading and writing of memory is performed using the cache memory line size. ”And“ Block Write ”are set.
The word length is an item that specifies the number of words at the time of a request for “Word Read” and “Word Write”. The address is
This item specifies the location of the memory to be accessed. The continuous instruction bit is an item for giving an instruction as to whether or not to process the next request continuously. This continuous instruction bit takes a value of “1” or “0” as shown in FIG.
Here, a description will be given assuming that “1” represents true and “0” represents false.

The memory 5 has a plurality of memory banks 51 to 5 each of which can independently hold a row address.
4 is provided. The memory 5 is, for example, a synchronous DR.
It can be constituted by AM or the like. Alternatively, it can be constituted by a normal DRAM and an attached circuit.

The memory control device 4 includes a memory 5 of each request device of the CPU 2, the input / output device 6, and the interprocessor communication device 7.
The arbitration circuit 41 includes a flag 42 indicating a continuous access state therein, a memory control circuit 43, and a selector 44.

Upon receiving an access request from each requesting device, the arbitration circuit 41 selects one of the requesting devices by arbitration, and indicates that the access request of the selected requesting device continuously processes a plurality of accesses. If the request is an access request, an access request from the requesting device is preferentially selected at the time of the next arbitration. To achieve this behavior,
The arbitration circuit 41 includes a continuous access state flag 42.

If the access request of the requesting device selected by the arbitration circuit 41 is a continuous access request, the continuous access status flag 42 contains information indicating that the device is in the continuous access state and specifies the requesting device. And if the request is not a continuous access request, information indicating that the access state is the normal access state.

The arbitration circuit 41 selects the next access request from the requesting device in accordance with the information held in the continuous access state flag 42. Upon selecting the access request, the arbitration circuit 41 sends a response signal C indicating the selection to the selected requesting device.

The selector 44 receives the command signal b from each requesting device, and selects the command signal b of the requesting device selected by the arbitration circuit 41 from these inputs. The memory control circuit 43 controls access to the memory 5 of the request device selected by the arbitration circuit 41 according to the command signal b selected by the selector 44.

Next, a memory control operation in the memory control system of the present embodiment will be described.

First, a procedure for issuing an access request from each of the requesting devices of the CPU 2, the input / output device 6, and the inter-processor communication device 7 will be described. FIG. 3 shows a procedure for issuing an access request when a plurality of accesses are processed continuously. Hereinafter, a case in which an access request for continuously processing n accesses will be described with reference to FIG.

The requesting device sets the continuous instruction bit (see FIG. 2) of the command signal b to "1" and issues an access request for the first access to the memory control device 4 (step S1). ). The second to n-1
In the same way, the access request is issued with the continuous instruction bit set to "1".
For the last n-th access, an access request is issued with the continuation instruction bit set to "0" (step S2). In the case of a normal access request (one that does not need to process a plurality of accesses consecutively), the requesting device sets the continuation instruction bit to “0” and issues the access request.

Next, the operation of the arbitration circuit 41 will be described.
FIG. 4 shows a control procedure of the arbitration circuit 41. Hereinafter, the control procedure will be described with reference to FIG.

In step S11, an access request from each requesting device is waited. When an access request is received from each requesting device in the access request waiting state, in subsequent step S12, the information held in the continuous access state flag 42 is checked to determine whether or not the apparatus is in the continuous access state. At this time, if the access request of the previously selected requesting device is a continuous access request, the continuous access status flag 42 holds information indicating that the device is in the continuous access status and information for specifying the requesting device. If the request is a normal access request, information indicating that the request is in the normal access state is held.

If the determination in the step S12 is a continuous access state, it is determined in a succeeding step S13 whether or not the current access request is from a continuous access device. If this determination is true, the access request is selected in the following step S14, and the process proceeds to step S16 described below. If false, the process returns to the request waiting state in step S11 described above.

If it is determined in step S12 that the access state is not the continuous access state, that is, if the access state is the normal access state, an access request is selected by an appropriate arbitration method in step S15, and the process proceeds to step S16 described later. The arbitration in step S15 is a well-known arbitration performed when a plurality of access requests are received at the same time, and a description thereof will be omitted here.

When an access request is selected in step S14 or S15, subsequently, in step S16, the continuation instruction bit is set to "1" for the selected access request.
It is determined whether the request is a continuous access request or not. If the access request is a continuous access request, information specifying the requesting device that issued the selected access request and information indicating the continuous access request are stored in the continuous access state flag 42 in step S17.
It returns to the request waiting state of No. 11. If the request is not a continuous access request, the information indicating that the request is a normal access request is stored in the continuous access state flag 42 in step S18, and the process returns to the request waiting state in step S11 described above.

In the memory control system of the present embodiment described above, when a continuous access request is selected, the next access can be performed while retaining the row address of the previously performed access. Therefore, the designation of the row address can be omitted for the second and subsequent access requests of the continuous access request, and the access can be speeded up accordingly. During this continuous access, no access request from another requesting device is accepted.

Since each requesting device always asserts an access request when there is a request, the arbitration circuit 41
Can select an access request according to the state of the memory control circuit 43. The delay in switching the access request is smaller than the delay in the conventional memory control described above.

In this embodiment, a parallel computer constituted by a plurality of processors has been described. However, the memory control of the present invention is not limited to this configuration.
For example, the present invention can be applied to a computer including a single processor.

Although a command signal line connecting each requesting device and the memory control device is provided for each requesting device, a connection structure using a bus or the like may be used instead.

Further, a configuration may be employed in which a plurality of request devices and a plurality of memory control devices are connected via switches.

(Other Embodiments) In the memory control system of the above-described embodiment, when a normal access request having a different page address is issued from another access request unit during continuous access, the access request is accepted. You can also. Here, a system that can realize the control operation will be described.

FIG. 5 is a block diagram showing the configuration of another embodiment of the memory control system of the present invention. The memory control system of the present embodiment has the same configuration as the memory control system shown in FIG. 1 except that a continuous access page register is added inside the arbitration circuit. In FIG. 5, the same components are denoted by the same reference numerals. Note that the description of the same configuration as that shown in FIG. 1 is as described above, and will not be repeated here.

In the memory control system of this embodiment, a continuous access state flag 42 and a continuous access page register 45 are provided inside the arbitration circuit 41 '. When the access request selected by the arbitration circuit 41 'is a continuous access request, the continuous access page register 45 stores the page address of the continuous access request (the page address of each access of the continuous access request is basically the same). Hold). In the present embodiment, when the requesting device currently permitting the access is in the continuous access state, the arbitration circuit 41 ′ transmits the page address from the other requesting device to the page address held in the continuous access page register 45. In contrast, when a normal access request that is not a continuous access request is issued, the access request is accepted and the access to the memory 5 is permitted. FIG. 6 shows a control procedure in the arbitration circuit 41 '. Hereinafter, the control procedure will be described with reference to FIG.

In step S21, an access request from each requesting device is waited. When an access request is received from each requesting device in the access request waiting state, in subsequent step S22, the information held in the continuous access state flag 42 is checked to determine whether or not the apparatus is in the continuous access state. If this determination is not a continuous access state, that is, if it is a normal access state, an access request is selected by an appropriate arbitration method in step S27, and the process proceeds to step S28 described later. The arbitration in step S27 is a well-known arbitration performed when a plurality of access requests are received at the same time, and a description thereof will be omitted here.

If the determination in the step S22 is a continuous access state, it is determined in a succeeding step S23 whether or not the access request is from the current continuous access device. If the access request is from the current continuous access device,
In a succeeding step S24, the access request is selected, and the process proceeds to a step S28 described later. If it is not an access request from the current continuous access device, the process proceeds to step S25,
The page address of the access request is different from the page address held in the continuous access page register 45,
Also, it is determined whether or not the continuous instruction bit is “0”. If this confirmation is true, the following step S26
In step S28, the access request is selected, and the process proceeds to step S28 described below. If the access request is false, the process returns to the request waiting state in step S21.

In step S28, it is determined whether or not the selected access request is a continuous access request. In the case of a continuous access request, in the following step S29, information for specifying the requesting device that has issued the selected access request and information indicating that the request is a continuous access request are stored in the continuous access status flag 42, and the page address of the access request is stored. Is stored in the continuous access page register 45, and the process returns to the request waiting state in step S11 described above. If the request is not a continuous access request, information indicating that the request is a normal access request is stored in the continuous access state flag 42 in step S30, and then the process returns to the request waiting state in step S11 described above.

With the above-described processing, interrupt control during continuous access can be performed, and processing can be performed without waiting for accesses other than the continuous page address of another requesting device.

In this embodiment, during continuous access,
An access request from another requesting device is accepted, but the accepted access request is a normal access request whose page address is different from the page address of the continuous access request. Therefore, in the memory 5, the page address of the continuous access request remains held, and the interrupt control during the continuous access does not hinder the increase in speed described in the previous embodiment.

[0057]

As described above, according to the present invention,
During a continuous access, an access request from another component is selected and the held row address changes, and there is no need to reset the row address, so that a series of accesses can be processed at high speed. In total, access requests from a plurality of access request devices can be efficiently processed.

Further, according to the present invention, a continuous access request can be indicated to the memory control device simply by setting the continuous instruction bit. Therefore, it is not necessary to perform special control such as confirming that the access request from each access requesting device can be switched to a smaller delay than before, and exclusive control can be performed efficiently.

Further, according to the present invention, it is possible to process access requests other than the continuous page address of other requesting devices without waiting, so that access requests from a plurality of access requesting devices are switched and processed at high efficiency. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory control system of the present invention.

FIG. 2 is a diagram showing a format example of a command signal b transmitted from each requesting device shown in FIG. 1;

FIG. 3 is a flowchart showing an access request issuing procedure performed by each requesting device shown in FIG. 1 when a plurality of accesses are processed continuously.

FIG. 4 is a flowchart for explaining the operation of the arbitration circuit 41 shown in FIG. 1;

FIG. 5 is a block diagram showing another embodiment of the memory control system of the present invention.

FIG. 6 is a flowchart for explaining the operation of the arbitration circuit 41 ′ shown in FIG. 1;

[Explanation of symbols]

 1-1 to 1-N processor 2 CPU 3 cache memory 4 memory control device 5 memory 6 input / output device 7 interprocessor communication device 8 interprocessor network 41 arbitration circuit 42 continuous status flag 43 memory control circuit 44 selector 45 continuous access page register 51-54 memory bank

Claims (7)

[Claims] 1. A memory control method for controlling access to a memory having a plurality of memory banks, each of which can independently hold a row address, wherein a plurality of access request devices capable of accessing said memory When an access request is received from the
Selecting one of the access requests to allow access to the memory, and determining whether the access request selected by the arbitration is a continuous access request indicating that a plurality of accesses are to be continuously performed, If the request is a continuous access request, at the time of the next arbitration, preferentially selecting an access request from the access request device that issued the continuous access request. 2. The memory control method according to claim 1, wherein when the result of the determination as to whether or not the request is a continuous access request is a continuous access request, information indicating that the access is continuous and said access request are transmitted. Information for identifying the issued access request device, and in other cases, information indicating that the device is in the normal access state, and based on the held information, the device is currently in the continuous access state. A memory control method, further comprising a step of determining whether or not the memory control is performed. 3. The memory control method according to claim 2, wherein, when the result of the determination as to whether or not the request is a continuous access request is a continuous access request, a step of holding a page address of the request; In the case where a normal access request is issued from an access request device other than the access request device currently performing continuous access, the page address is different from the held page address, and is not a continuous access request, A memory control method, further comprising the step of accepting the access request and permitting access to the memory. 4. A memory means having a plurality of memory banks each capable of independently holding a row address; a plurality of access request means capable of accessing the memory means; and a plurality of access request means. And a memory control means for selecting any one of the access requests by arbitration and permitting access to the memory means. Is performed, a continuous access request indicating that fact is issued, and the memory control unit, if the access request unit that has issued the continuous access request permits access to the memory unit, the next time, A memorandum configured to preferentially select an access request from the access request means at the time of arbitration. Control system. 5. The memory control system according to claim 4, wherein the memory control unit arbitrates an access request issued from a plurality of access request units, and the memory control unit is selected by the arbitration unit. When the access request is a continuous access request, information indicating that the access request is in a continuous access state and information for specifying an access request unit that has issued the access request are held. Flag means for holding information indicating that the memory control means is in a continuous access state based on the information held in the flag means; In the case of the access state, it is configured that, at the time of the next arbitration, the access request from the access request means that is currently performing continuous access is preferentially selected. Memory control system, characterized in that the. 6. The memory control system according to claim 5, wherein each of the plurality of access request means includes a command signal including a continuous instruction bit indicating whether or not to perform a plurality of accesses continuously, together with the access request. A memory configured to transmit to the control means, and wherein the flag means is configured to take one of a continuous access state and a normal access state based on the information of the continuous instruction bit. Control system. 7. The memory control system according to claim 6, wherein the memory control means includes, when the access request selected by the arbitration means is a continuous access request, a register means for holding a page address of the request. The arbitration means, when the memory control means is in a continuous access state, a page whose page address is held in the register means from an access request means other than the access request means which is currently performing continuous access; A memory control system characterized in that when a normal access request different from an address and not a continuous access request is issued, the access request is accepted and access to the memory means is permitted.