JP3496942B2 - Memory access method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method when an MPU accesses a buffer memory via a memory control circuit. In recent electronic control circuits,
In some cases, the MPU accesses a memory (for example, a data buffer or the like) that is not on the same data bus via a peripheral circuit (for example, a memory control circuit or the like) of the MPU. The present invention adds a simple circuit to the memory control circuit so that any access instruction in units of bytes, words, or longwords provided in the MPU can be implemented.
The present invention relates to a memory access method that performs an auto-increment operation and enables an MPU to execute access processing to a single or continuous area of a memory. 2. Description of the Related Art FIG. 4 is a block diagram of a control circuit of a magnetic disk drive in a data processing system. In the figure, an upper MPU 11 controls and manages the lower MPU 18 and controls data transfer with the upper host device.
Reference numeral 12 denotes a ROM which stores programs of two MPUs (11, 18). Reference numeral 13 denotes a RAM, which is a work RAM for storing data used when the program of the ROM 12 is operated. [0005] Reference numeral 14 denotes a buffer controller, which is a circuit for controlling the data buffer 16. Reference numeral 15 denotes an upper interface for performing data transfer with an upper host. A data buffer 16 stores data sent from the host computer and data read from the magnetic disk 17. 17 is a magnetic disk drive. 1
A lower MPU 8 controls and manages the magnetic disk device 17. Reference numeral 19 denotes a communication control circuit, which is an upper MPU 11
And a control circuit for performing communication between the lower MPU 18. Reference numeral 20 denotes a RAM which stores a program of the lower MPU 18 and has a function as a work RAM. In this magnetic disk device control circuit, a data buffer (RAM) 16 is provided to improve the efficiency of data transfer between the upper interface 15 and the magnetic disk 17.
Is provided, but as shown in FIG.
And the MPU 11 are connected to separate data buses (a) and (b).
6 cannot be accessed. However, when executing an error correction process or under special circumstances such as reading system information on the device from the magnetic disk device 17, the MPU 11 accesses the data buffer 16 and the data buffer 16 is accessed via the buffer controller 14. It is required to perform processing. Although two MPUs 11 and 18 coexist, the work RA of the lower
For M20, the upper MPU 11 may load the program of the lower MPU 18 from the ROM 12. Also in this case, the MPU 11 and the work RAM 20 are connected to the data bus.
(a) and a data bus (c), which are not on the same data bus.
It is required to perform access processing through. Therefore, the buffer controller 14 and the communication control circuit 19 include:
When accessing a memory (buffer memory) that does not exist on the same bus as the MPU, a buffer memory control means (memory control circuit) that controls so that an area of an address specified by the MPU is appropriately accessed. Must be provided. FIG. 5 is a diagram illustrating an example of a conventional addressing system. This figure illustrates a method in which the MPU 1 accesses the buffer memory 3 via the memory control circuit 2. A 1-byte register (memory access register) 22 that can be directly accessed from the MPU 1 in the memory control circuit 2 and corresponds to the memory area of the address specified by the address register 21 in the memory control circuit 2 as a virtual area After setting and specifying the memory address,
When the PU1 accesses the memory access register 22, the processing is actually performed in the memory area (1 byte) of the designated address corresponding to the register. When accessing a continuous memory area by this method, the address specification and the access processing to the memory access register 22 must be repeated one byte at a time. That is, in the case of a long word, the address is specified as address P → P + 1 → P + 2 → P + 3.
The access is performed once, and the processing is performed in the order of 1 byte area a → b → c → d corresponding to the address of the buffer memory 3. FIG. 6 is a diagram for explaining another example of the conventional addressing system. This figure is an explanatory diagram for coping with the above-mentioned conventional method. As shown in the figure, a mode setting register 23 is provided in the memory control circuit 2 and a memory access mode is set.
Access to the continuous memory area can be facilitated by adding a mode in which the value indicated by the address register 21 is incremented by one (auto increment permission mode) at the same time when the register 22 is accessed. In the configuration shown in FIG. 6, although the mode setting function eliminates the need for address specification, the MPU 1 can output 2 bytes (words) to 4 bytes (long words). Even though the access is possible, it is necessary to repeat the access for each byte. That is, in the case of a long word, in the auto-increment permission mode, the head address P is specified, the memory access register 22 is accessed four times, and the processing is performed in the order of a → b → c → d in the address area. Thereafter, auto increment is performed in the order of P + 1 → P + 2 → P + 3. Therefore, even if the MPU needs to access a plurality of continuous memory areas, the memory can be accessed only one byte at a time.
As described above, the access processing is repeatedly performed one byte at a time from the start address, and thus a problem arises that it takes time. [0010] An object of the present invention is to change the configuration of a memory access register in a memory control circuit so that M
An auto-increment operation is performed for any access instruction in units of bytes, words, or longwords provided in the PU, enabling the MPU to execute access processing to a single or continuous area of the memory. To provide a memory access method that performs FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, reference numeral 1 denotes an MPU that manages and controls a circuit. Further, data processing can be performed in byte, word, or longword units. Reference numeral 2 denotes a memory control circuit, and access from the MPU 1 to the buffer memory 3 is executed through the memory control circuit 2. 3 is a buffer memory. 21 is an address register;
When the address of the memory area accessed by PU1 is specified, the value is stored. Reference numeral 22 denotes a plurality of bytes (for example, 4 bytes) of memory access registers (A to D). This register area is a virtual area actually accessed by the MPU 1 when the MPU 1 accesses the buffer memory 3, and one byte (BYTE) of the memory access register corresponds to a one-byte memory area. In the memory access register 22, MP
According to the unit of access of U1, processing is performed singly or successively one byte at a time from the first accessed register. A mode setting register 23 designates whether or not the address register 21 permits the auto-increment function. Address register 21
After the address of the buffer memory 3 is stored in the MPU,
When 1 accesses any of the memory access registers 22 (usually the first byte),
The processing is executed for the area of the address specified by the memory access register 21 in the memory 3. When the auto increment mode is set by the mode setting register 23, the value of the address register 21 is incremented by 1 each time the MPU 1 accesses one byte of the memory access register 22. According to the present invention, when the MPU 1 accesses the buffer memory 3, the mode setting register 23 of the memory control circuit 2 is set to the auto-increment permission mode, and the start address P of the buffer memory 3 is designated. Later, when any one of the (usually the first byte) A of the memory access register 22 is accessed, that memory
The processing of the memory area at the address designated corresponding to the access register 22 is executed one byte at a time, and at the same time, the value of the address register 21 is counted by one (P +
1), if the address counter 21 is continuously processed by one byte in accordance with the access unit from the MPU, the next successive memory area is processed by one byte in accordance with the instruction of the address incremented by one. To be executed one by one. That is, the memory access register is A →
In the order of B → C → D, processing is performed in the order of bytes (BYTE) 1 → 2 → 3 → 4, and in the buffer memory, addresses P → P + 1 → P
Processing is performed in the order of + 2 → P + 3 in the order of areas a → b → c → d. Therefore, even when the MPU 1 issues an access to consecutive bytes of the memory in the buffer memory 3,
It is possible to execute a plurality of bytes of processing corresponding to an access unit from an address specified by one access instruction without repeatedly specifying an address or issuing an access instruction by the number of bytes. FIG. 2 is a block diagram showing an embodiment of a memory control circuit according to the present invention. As described above, the MPU 1 can access the buffer memory 3 via the memory control circuit 2. The MPU 1 can execute data control in byte, word, and longword units. Memory control circuit 2
2a, an address decoder 2a selects a register to be operated by the MPU 1 in accordance with a register address instruction from the MPU 1. address·
Among the select signals (SELECT) output from the decoder 2a, SELECT 1─4 is a register (memory access register 22 in FIG. 1) set imaginarily to correspond to the memory area to be accessed by the MPU 1. Each byte corresponds to one byte (a total of four bytes). When an address indicating a memory access register is designated by an access instruction of the MPU 1, the address decoder 2a sets the output of SELECT 1 to 1, and the designation of the address is updated when processing a plurality of consecutive bytes. Each time, the output is set to 1 in the order of SELECT 1 → 2 → 3 → 4. SE
LECT5 corresponds to the address register 2b, and SELECT6 corresponds to the mode setting register 2c. 2b is an address register, and the MPU in the buffer memory 3
1 is stored. When the * LOAD input is 0 in the address register 2b, the address register 2b stores the address value sent by the MPU 1 to the data bus. At the rising edge when the COUNT UP input of the address register 2b becomes 1, the address
The count value of the register 2b increases by one. Reference numeral 2c denotes a mode setting register for setting whether or not the address register 2b is in the auto increment permission mode. * LOAD in address register 2b
When the input is 0, the set value from MPU1 is set.
When the increment mode output (INCREMENT MODE) is 1, the automatic increment permission mode is set. 2d is O
R circuit and RAM select output (RAM SELECT) is 1
If (ie, * RAM SELECT output is 0), the buffer memory 3 is in the selected state. Numeral 2e denotes a NAND circuit, in which the output becomes 1 if the signal RAM SELECT is 0 in the auto increment permission mode. FIG. 3 is a signal timing chart of one embodiment of the present invention. When the MPU 1 accesses the memory buffer 3 via the memory control circuit 2, it operates as follows. The illustrated timing chart is a timing chart when the MPU 1 performs write access in units of long words in the configuration of FIG. When the access may be made in word or long word units, the setting of the mode setting register 2a is set to the auto increment permission mode. The MPU 1 loads the head address of the memory area to be accessed to the address register 2b, and starts accessing a memory access register virtually set in longword units. The MPU 1 transfers the address of the memory access register to the MPU address bus and the buffer memory 3
Data to be written to the MPU data bus. At this time, between the MPU 1 and the memory control circuit 2, the processing for each byte is continuously performed (in the case of access in units of long words, the byte processing is performed four times). Address decoder 2
When a receives the head address of the memory access register, it sets the output of SELECT1 to 1. When SELECT1 becomes 1, SELECT1 becomes
-4 is obtained through the OR circuit 2d. The signal RAM SELECT is 1 (*
RAM SELECT is 0) and buffer memory 3 is MPU
1 is selected as the access target. M
PU1 outputs a write strobe signal (* WT STROBE0) to the memory access register, and this signal is directly input to the buffer memory 3 via the memory control circuit 2 as a write enable signal (* WT ENABLE). * WT
The first 1-byte data sent from the MPU 1 while ENABLE is 0 is written to the head address area of the buffer memory 3. After the write processing, the signal * WT STROBE (* W
TENABLE) becomes 1, and the MPU 1 updates the address designation of the memory access register to the next byte area by seeing the change of this signal. By changing the address, SELECT1 of the address recorder 2b becomes 0, and then SELECT
RAM SELECT becomes 0 until 2 becomes 1. This RAM SELE
At the fall of CT, the output of the NAND circuit 2e (that is, the COUNT UP input of the address register 2b) becomes 1, and the address value of the address register 2b (the address of the buffer memory) is set to the address next to the head address. You. For the area of the address updated in this way, the MPU 1
The succeeding 1-byte write process is executed by the process of the byte, and the write process for the remaining buffer memory 3 is also processed for each byte in the same procedure. Although the above embodiment is directed to write access in units of long words, it is apparent that similar effects can be obtained in other access instructions (read etc.) and even in access instructions in word units. It is. In the present embodiment, the data bus between the MPU and the memory control circuit and the data bus between the memory control circuit and the buffer / memory are byte buses. It can be analogized and does not depart from the gist of the present invention. As described above, according to the present invention, M
When accessing the buffer memory from the PU via the memory control circuit, not only access in byte units, but also
MPU by word or longword access
Since it is possible to process the continuous byte area from the address designated by the MPU, it is possible to make the access processing capability of the MPU function sufficiently efficiently, which greatly contributes to the improvement of the processing performance of the entire apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle configuration diagram of the present invention. FIG. 2 is a configuration diagram of an embodiment of the present invention. FIG. 3 is a signal timing chart of one embodiment of the present invention. FIG. 4 is a configuration diagram of a control circuit of the magnetic disk drive. FIG. 5 is a diagram illustrating an example of a conventional addressing method. FIG. 6 is an explanatory diagram of another example of the conventional addressing method. [Description of Signs] 1 MPU 2 Memory control circuit 3 Buffer memory 21 Address register 22 Memory access register 23 Mode setting register 2a Address decoder 2b Address register 2c Mode setting register 2d OR circuits 11, 18 MPU 12 ROM 13 RAM 14 Buffer controller 15 Upper interface 16 Data buffer 17 Magnetic disk device 19 Communication control circuit 20 RAM

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-1-310463 (JP, A)                 JP-A-61-217842 (JP, A)                 JP-A-60-261095 (JP, A)                 JP-A-1-144139 (JP, A)                 JP-A-61-262861 (JP, A)                 JP-A-2-162449 (JP, A)                 JP-A-61-265653 (JP, A)

Claims (1)

(57) [Claims] [Claim 1] MPU (1) and buffer memory (3)
The memory control circuit (2) is arranged between the MPU (1)
Accesses the buffer memory (3) via the memory control circuit (2) and processes the data one byte at a time.
In the access method, the buffer memory (3) accessed by the MPU (1) in the memory control circuit (2)
Address address corresponding to the address is stored,
A register (21), a virtual area to which an instruction is issued when the MPU (1) accesses the buffer memory (3), wherein each byte of the virtual area is the address register (21);
And a plurality of memory access registers (22) configured to correspond to an area of one byte in the buffer memory (3) specified by Mode setting register (2
When the mode setting register (23) is set to the auto-increment permission mode, the MPU (1) accesses one of the memory access registers (22), and When the processing in the memory area at the address specified by the register (21) is executed, the value of the address register (21) is increased by one, and the plurality of memory access registers (22) On the other hand, when the MPU (1) issues an access instruction so as to process continuously, the address increases by one for each one-byte processing of the memory area corresponding to the memory access register (22). to, by successively with 1 degree access command to be executed to process the next 1-byte memory area designated of the buffer memory (3) in It was started from the address for accessing the plurality consecutive bytes, a memory access method, characterized in that
Law .