JPH10187359A - System for storing data and method for transferring data applied to the same system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize data transfer independent for each flash EEPROM by providing a data bus for each flash EEPROM in a system using a semiconductor disk device. SOLUTION: A data storage system using a semiconductor disk device constituted of flash EEPROM is provided with data buses A and B provided for each flash memory 2A and 2B, and a controller 4 connected with each bus A and B for controlling the transfer of input and output data for each flash memory 2A and 2B. Thus, the controller 4 can transfer the input and output data independently for each flash memory 2A and 2B so that an average transferring speed especially at the time of a data writing operation can be quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage system applied to a computer system and using a semiconductor disk device composed of a flash EEPROM.

[0002]

2. Description of the Related Art Conventionally, in a computer system, unlike a main memory, an external storage device which retains data when power is turned off and has a large-capacity data storage function is an essential component. As this external storage device, a flash EEPROM that can be accessed at a higher speed than a magnetic disk device or an optical disk device, etc.
(Semiconductor disk devices) composed of (flash memories) are attracting attention.

A semiconductor disk device generally includes a plurality of flash EEPROM memory chips, a controller, and a buffer RAM. The controller is an interface between the host system and each flash EEPROM, and executes read / write control of each flash EEPROM in response to an access request from the host system. The buffer RAM is a buffer memory for transferring data between the host system and the controller, and stores the write data transferred from the host system and the read data read from each flash EEPROM.

[0004]

As described above, in the semiconductor disk device, the controller forms an interface between the host system and each flash EEPROM and controls the transfer of input / output data (read / write data). is there. Incidentally, data transfer between the controller and each flash EEPROM is normally performed by one data bus.

In a flash EEPROM, a writing operation (including an erasing operation) is slower than a data reading operation. For this reason, especially during data write operation, in data transfer by one data bus, each flash EEP
The processing efficiency when accessing the ROM continuously decreases remarkably.

Accordingly, an object of the present invention is to provide a flash EEP in a system using a semiconductor disk device.
A data bus is provided for each ROM or each group of a plurality of flash EEPROMs, and each flash EEPROM is provided with a data bus.
An object of the present invention is to make it possible to transfer data for each ROM and to improve the efficiency of access processing particularly during a data write operation.

[0007]

SUMMARY OF THE INVENTION The present invention provides a flash E
In a data storage system using a semiconductor disk device composed of an EPROM, for example, when one group is composed of a plurality of flash EEPROMs, a plurality of data buses provided for each group and a plurality of data buses connected to each data bus are provided. This is a system including a controller for controlling transfer of input / output data for each flash EEPROM. With such a configuration, the controller can transfer input / output data independently for each flash EEPROM, so that access efficiency particularly in a data write operation can be improved.

Further, the present invention assumes a configuration in which the controller and the buffer memory (buffer RAM) are connected by one bus. The buffer memory includes data (write data) transferred from the host system and each flash EEPROM transferred from the controller.
The data (read data) read from the memory is stored. At the time of data write operation, the controller
Data transfer is performed independently on the data bus of each EPROM, but it is necessary to control data transfer from the buffer memory via one bus.

Therefore, the controller of the present invention has a bus register in which the first and second registers are combined for each data bus, and connects to the buffer memory in response to a data transfer request for each data bus means. Means for executing bus arbitration by time-division transfer on one of the selected buses. At this time, the data transfer control for the data bus is executed by using the first and second registers provided for each data bus alternately. Thus, at the time of data write operation, independent data transfer to each flash EEPROM and time-division transfer control data transfer from the buffer memory are realized, thereby improving data transfer efficiency and consequently providing access during data write operation. Processing efficiency can be improved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of a semiconductor disk device according to an embodiment of the present invention. (System Configuration) The semiconductor disk device 1 of the present embodiment is roughly classified as shown in FIG.
(Hereinafter referred to as flash memories) 2A and 2B, a controller (disk controller) 4, and a buffer RA
M (buffer memory) 8. Here, each of the flash memories 2A and 2B includes a group of memory chips when one group includes a plurality of flash EEPROMs.

Each of the flash memories 2A and 2B has an EEPR
In addition to the OM memory cells, the data registers 12A, 12A
B, and input / output data (I / O) is transferred using the data registers 12A and 12B as buffers. Each of the flash memories 2A and 2B outputs a busy (BUSY) signal at the time of data read / write in response to a read access or a write access, and outputs a ready (READY) signal if the read / write is possible (R
/ B signal). Further, in the present invention, each flash memory 2 is used as a data bus 3 for transferring input / output data.
Data buses A and B are provided for each of A and 2B.

The controller 4 is roughly divided into a data transfer block 5 and a microprocessor (MPU) block 6
And an interface 7 with the host system. The data transfer block 5 executes data transfer between the buffer RAM 8 and each of the flash memories 2A and 2B under the control of an MPU block (hereinafter simply referred to as MPU) 6. Control signals (such as an R / B signal and a chip select signal CE) necessary for this data transfer operation are exchanged between the flash memories 2A and 2B. further,
As described above, the data transfer block 5 has dedicated data buses A and B with the flash memories 2A and 2B, respectively.
, Input / output data (read / write data) is transferred (serial data transfer). The data transfer block 5 performs data transfer with the buffer RAM 8 via one bus 9 as described later.

The MPU 6 is a main control device of the semiconductor disk device 1 and executes a program stored in a ROM (not shown) to read / write data from / to the host system.
Performs various control operations such as write command processing (also called firmware together with programs). Specifically, the MPU 6 controls the data transfer block 5, the interface 7, and the buffer RAM 8 in response to an access request from the host system to control data transfer with the host system. The interface 7 transfers data transferred from the host system to the buffer RAM 8, and the data transfer block 5
8 is transferred to the host system.

The host system is a computer main unit connected to a peripheral device such as the semiconductor disk device 1 via an external bus. Here, it is assumed that the semiconductor disk device 1 is used as a peripheral device of an external storage device. I have. (Data transfer operation of the present embodiment) In the system configuration as described above, in the controller 4, the data transfer block 5 executes data transfer between the buffer RAM 8 and each of the flash memories 2A and 2B according to the instruction of the MPU 6. Here, it is assumed that the flash memories 2A and 2B are two memory chips for convenience.

In this embodiment, the controller 4 communicates with the flash memories 2A, 2A via dedicated data buses A, B.
Data transfer is performed independently of 2B. Here, as shown in FIG. 2, the data transfer block 5 has a group of registers necessary for the data transfer operation. The register group is provided for each of the data buses A and B, and the data start address register 20 in the buffer RAM 8 is respectively provided.
A, 20B, data start address registers 21A, 21B on the flash memory side, data transfer direction instructing registers 22A, 22B, data transfer monitoring register 23
A, 23B. The data transfer monitoring registers 23A and 23B are registers that hold flag information for recognizing a data transfer state (operating or ended).

The MPU 6 sets control information such as an address, a direction instruction, and a data transfer state flag in these registers, and executes data transfer control by referring to the set control information. In other words, the data transfer block 5 independently transfers data without interfering with the data buses A and B under the control of the MPU 6 through the register group provided for each of the data buses A and B. Do.

The data buses A and B of the flash memories 2A and 2B are usually 8-bit buses, whereas the bus 9 of the buffer RAM 8 is a double 16-bit bus. Therefore, if each of the data buses A and B operates in the same cycle with respect to the bus 9 of the buffer RAM 8, the transfer speed difference becomes twice. Further, as described above, since the data transfer speed in the data write operation to the flash memories 2A and 2B is low, the speed difference further increases the data transfer average speed difference in the data write operation.

In this embodiment, independent data transfer operations are performed by the data buses A and B provided exclusively for the flash memories 2A and 2B. Thus, the data transfer speed of the flash memories 2A and 2B can be increased as compared with the case of a single data bus as in the related art. In particular, the flash memory 2A,
Data write operation to 2B (write access)
In the prior art, it is possible to considerably reduce the difference in average data transfer speed with respect to the transfer speed of the bus 9 of the buffer RAM 8. (Bus Arbitration of Buffer RAM) As described above, according to the present embodiment, the flash memories 2A, 2A
Data buses A and B provided exclusively for each B enable independent data transfer. Therefore, the data transfer speed between the data transfer block 5 and the flash memories 2A and 2B is particularly increased during a data write operation. be able to.

During a data write operation, the data transfer block 5 transfers write data from the buffer RAM 8 and transfers the write data to the flash memories 2A and 2B. The buffer RAM 8 is normally connected to the data transfer block 5 by one bus 9. Therefore, MP
When transferring data independently to the data buses A and B, U6 transfers the data from the buffer RAM 8 via the same bus 9, so that bus arbitration (bus arbitration) for avoiding interference on the bus 9 is performed. Function).

The data transfer method of the bus 9 of the buffer RAM 8 according to the present embodiment will be described below with reference to the conceptual diagram of FIG. 3, the timing chart of FIG. 4, and the flowchart of FIG.

First, in the present embodiment, as shown in FIG.
The data transfer block 5 has first and second registers dedicated to the data buses A and B, respectively. The first and second registers corresponding to the data bus A are referred to as a bus A0 register and a bus A1 register, respectively. Similarly, data bus B
Are referred to as a bus B0 register and a bus B1 register, respectively. Each register is, for example, 16 words.

If a transfer request for the data bus A occurs, the data transfer block 5 transfers data from the buffer RAM 9 to the bus A0 register if the transfer on the bus 9 is possible (steps S1 to S3). Next, if the transfer on the bus 9 is possible in response to the transfer request on the data bus A, the data is transferred from the buffer RAM 9 to the bus A1 register (steps S4 to S6). At this time, the data transfer block 5 transfers the data held in the bus A0 register to the data bus A (Step S).
7). Such processing is repeated unless there is a transfer request for the data bus B. That is, the buffer RA is used by alternately using the bus A0 register and the bus A1 register.
The data transferred from M9 is transferred to data bus A.

On the other hand, when a transfer request for the data bus B occurs, if the transfer on the bus 9 is possible, the data is transferred from the buffer RAM 9 to the bus B0 register (steps S8 to S10). Here, as shown in FIG.
The transferable time is divided into two equal parts by time division, and if there is a transfer request in the transferable time (time indicated by yes), data transfer is executed. Therefore, when a transfer request for the next data bus B occurs, if the transfer time is not the transfer time as the bus B (the time indicated by no), the data transfer from the buffer RAM 9 to the bus B1 register will not be executed. (NO in steps S11 and S12).

In short, as shown in the timing chart of FIG. 4, the transferable time (yes) divided into two equal parts
), A transfer request for each of the data buses A and B is generated.
The data is transferred to one of the register, the bus B0 register, and the bus B1 register. Similarly, when data is transferred to the bus B1 register on the data bus B, the data transfer block 5 transfers the data held in the bus B0 register to the data bus B (steps S13 and S14). ). Therefore, the data transferred from the buffer RAM 9 is transferred to the data bus B by using the bus B0 register and the bus B1 register alternately.

As described above, according to the present embodiment, independent data transfer operations can be executed by the data buses A and B provided exclusively for the flash memories 2A and 2B. Therefore, the average transfer speed to the flash memories 2A and 2B can be increased particularly during the data write operation. Thereby, the access efficiency to the flash memories 2A and 2B can be improved.

Here, the data transfer to and from the buffer RAM 8 is performed on one bus 9 by executing bus arbitration by time division transfer for each of the data buses A and B, so that the data is independent from the data buses A and B. Even if a transfer request occurs, it prevents a situation where interference occurs on the bus 9,
Data from the buffer RAM 8 can be reliably transferred to each of the data buses A and B.

[0027]

As described in detail above, according to the present invention, in a system using a semiconductor disk device, a data bus is provided for each flash EEPROM, and independent data transfer can be realized for each flash EEPROM. Therefore, particularly during a data write operation, the average transfer speed for each flash EEPROM can be increased, and the efficiency of access processing can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a semiconductor disk device according to an embodiment of the present invention.

FIG. 2 is an exemplary conceptual diagram showing the internal configuration of a controller related to the embodiment.

FIG. 3 is an exemplary conceptual diagram showing the internal configuration of a controller related to the embodiment.

FIG. 4 is a timing chart for explaining an operation related to the embodiment.

FIG. 5 is a flowchart for explaining an operation related to the embodiment;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor disk device 2A, 2B ... Flash EEPROM (flash memory) 3 ... Data bus (Data bus A, B) 4 ... Controller 5 ... Data transfer block 6 ... MPU block 7 ... Interface 8 ... Buffer RAM 9 ... Bus (buffer) RAM side bus) 20A, 20B ... data start address register (buffer RAM side) 21A, 21B ... data start address register (flash memory side) 22A, 22B ... data transfer direction instruction register 23A, 23B ... data transfer monitoring Register

Claims (8)

[Claims] 1. A data storage system using a semiconductor disk device composed of a plurality of flash EEPROMs, which is provided independently for each of the flash EEPROMs and transfers input / output data to and from the flash EEPROMs. And a plurality of data bus means connected to each of the data buses, and each of the flash EEPROMs in response to a read / write request from a host system.
A data storage system comprising: controller means for controlling access for each OM and controlling transfer of the input / output data. 2. An interface means for transferring data to and from the host system, storing data transferred from the host system via the interface means, and transferring data from the controller means. Buffer memory means for storing the data stored therein, and the controller means is connected to the buffer memory means by a single bus so as to transfer the data stored in the buffer memory means to the designated flash EEPROM. The data storage system according to claim 1, further comprising a control unit. 3. The controller means has a register group for controlling data transfer. The register group includes registers for monitoring a data transfer start address, a data transfer direction, and a data transfer state. 2. The data storage system according to claim 1, wherein said data storage system is provided for each data bus means. 4. A data storage system using a semiconductor disk device composed of a plurality of flash EEPROMs, provided independently for each of said flash EEPROMs, for transferring input / output data to and from said flash EEPROMs. A plurality of data bus means, buffer memory means for temporarily storing input data transferred from a host system or output data read from the flash EEPROM, and each of the flash memories via each of the data buses. EEPRO
M, and a data transfer means connected to the buffer memory means via one bus to execute transfer of input / output data between the buffer memory means and each of the flash EEPROMs; A read / write command from the host system is processed to control read / write access to each of the flash EEPROMs, and controls the buffer memory means and the data transfer means to control data transfer with the host system. A data storage system comprising: 5. An interface means for transferring data between the host system and the buffer memory means, wherein the control means is responsive to a write access request from the host system via the interface means. The input data transferred from the host system is stored in the buffer memory means, and an output from the flash EEPROM stored in the buffer memory means by the data transfer means in response to a read access request from the host system. 5. The data storage system according to claim 4, wherein control is performed so that data is transferred from said host system via said interface means. 6. The data transfer means has a bus register as a set of first and second registers for holding data output from the buffer memory means for each of the data bus means, Means for executing bus arbitration by time-division transfer on one bus connected to the buffer memory means in response to a data transfer request for each of the data bus means, and transferring from the buffer memory means by permitting data transfer 5. The data according to claim 4, further comprising means for transferring the obtained data to said data bus means to be accessed by using said first and second registers corresponding to said data bus means alternately. Storage system. 7. A data transfer method applied to a data storage system using a semiconductor disk device composed of a plurality of flash EEPROMs, wherein the data transfer method is provided independently for each of the flash EEPROMs, and is provided for each of the flash EEPROMs. A plurality of data buses A and B for transferring output data; buffer memory means for temporarily storing input data transferred from a host system or output data read from the flash EEPROM; Input / output data between the buffer memory means and each of the flash EEPROMs is connected to each of the flash EEPROMs via data buses A and B and to the buffer memory means via one bus. Data transfer means for executing the transfer of Over data transfer means said data bus A, bus register A0 for holding data output from said buffer memory means for each B, A1 and bus registers B0, B
1 when transferring data from the buffer memory means to data buses A and B corresponding to the flash EEPROM to be accessed in response to a write access request from the host system. Time-divided one bus transferable time of the buffer memory means, and transfers the data transferred from the buffer memory means when the buffer memory means can transfer the bus in response to the transfer request of the data bus A. A process for storing data in A0; storing data transferred from the buffer memory means when the buffer memory means can perform bus transfer in response to a transfer request of the data bus A in the bus register A1; A1 for transferring data from any one of the data buses A, A process of storing data transferred from the buffer memory means in the bus register B0 when the buffer memory means can perform a bus transfer in response to a transfer request of the bus B; Storing the data transferred from the buffer memory means in the bus register B1 when the means is capable of bus transfer, and transferring data from the bus register B0 or B1 to the data bus B. Data transfer method. 8. A flash EE comprising a plurality of flash EEs.
2. The data bus means comprising a PROM, wherein the data bus means is provided independently for each group.
A data storage system according to any one of claims 1 to 6.