JPH0381854A - Memory access system - Google Patents

Abstract

PURPOSE:To execute high speed memory access with the high degree of freedom by using address information and data written in an address memory part and a data memory part to be exclusively set up at the time of executing direct memory access (DMA). CONSTITUTION:When a memory control part (MCC) is started from a CPU 8 at the time of executing direct memory access (DMA), the MCC 6 controls the start and end positions of addresses in an address memory address control part (ANAC) 5 through the control line 60. Then MCC 6 requests DMA to the CPU 8 through a bus interface part (BIF) 1, DMA control lines 30, 31 and CPU bus 7 to release the bus 7. Since the address '0' is specified from the AMAC 3 to an address memory part (AM) 2 through an address line 50, the address information A0 is outputted from the AM 2 to the bus 7 through the BIF 1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory access method.

[Conventional technology]

In conventional memory access methods, writing and reading are performed in the main memory circuit etc. by commands from the main control circuit, or writing and reading are performed in consecutive addresses using direct memory access (DMA). .

[Problem to be solved by the invention]

In the conventional memory access method described above, in the former case, the execution speed is slow because it takes time to fetch and execute the instruction. Furthermore, in the latter case, although the execution speed is fast, since it can only support continuous addresses, there is a problem that high-speed and highly flexible memory access cannot be performed.

[Means to solve the problem]

The memory access method of the present invention includes first means connected to a common bus to which at least a main control circuit and a main memory circuit are connected, and for storing address information to be output to the bus; a third means for inputting/outputting data to/from the bus; and a third means for inputting/outputting data to/from the bus; a fourth means for instructing a storage address location; and a fourth means for transmitting a direct memory access control signal and a read/write control signal to the bus, and a fourth means for instructing the first. Second. and fifth means for controlling the third and fourth means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIGS. 1 and 2 showing one embodiment of the present invention, this memory access system is implemented by a main control circuit (CPU).
A bus interface unit (BIF) 1 that performs contention control for a common bus (CPU bus) 7 connected to the CPU 8;
An address memory section (AM) 2 that stores address information to be output to the U bus 7, an address memory address control section (AMAC) 3 that instructs the address position of the address information that is to be output stored in the AM 2, and a CPU bus. a data memory unit (DM) 4 that inputs and outputs data to and from the DM 7; and a data memory address control unit (DMAC) that instructs the storage address position of data to be input and output to the DM 4.
5, and a memory control unit (MCC) that controls each part.
It consists of 6. The main memory circuit (M
EM)9 etc. are connected.

In this configuration, it is assumed that address information and data called Ax and Dy (x, y are address values) are stored in AM2 and DM4, respectively, as shown in FIG. During DMA (for example, when writing data to MEM9), MCC6 controls the start and end positions of the address for AMAC3 via control line 62 upon activation from CPU8.At this time, MCC6 simultaneously controls DMAC5.
The start and end positions of the address are controlled via the control line 60. In this example, from MCC6 to AM
It is assumed that the AC3 is designated with a start position O and an end position n, and the DMAC5 is designated with a start position O and an end position n. MCC6 is B
A DMA request is made to the CPU 8 via IFl, the DMA control lines 30 and 31, and the CPU bus 7.
will be opened. Subsequently, AM2 is sent from AMAC3 to CPU bus 7 via BIFI at address 1150.
Since address O is specified in AM2, address information AO is output from AM2. At the same time, since the address O is designated from the DMAC5 to the DM4 by the address line 51, the data DO is output from the DM4. At this time, M
Read/write control line 40 from CC6 to CPU8
．． 41 is enabled and MEM connected to CPU bus 7.
Data Do is written to address AO of 9. After this,
MCC6 instructs AMAC3 and DMAC5 to output the next address, that is, address 1 is output, so address information A1 from AM2 and data D1 from DM4 are output to CPU bus 7. . Thereafter, the process is repeated in the same way until the address reaches n. In addition,
Start address 0 and end address O for DMAC5
If specified, data Do can be written to all addresses Ao-Aa of MEM9.

In Figure 1, 10.11 is the address line, 20°21
is the data line, 61.63 is the DM4. 0 or more MEM9, which is a control line used when rewriting the memory contents of AM2
We have described the data write operation to MEM9, but when reading data stored in MEM9 and writing it to DM4,
Enable the read/write control lines 40 and 41 from CC6 (set them to read status 1, and control AM2 and AMAC3 to set M
The address of EM9 is specified, and read data from MEM9 is sequentially written to the address of DM4 specified by DMAC5 via data lines 20, 21 and BIFI.

〔Effect of the invention〕

As explained above, according to the present invention, when performing DMA, address information and data written in a dedicated address memory section and a data memory section, which can be set arbitrarily, are used to perform DMA at high speed and with a high degree of freedom. can perform high memory access.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
It is a figure which shows the memory content of AM and DM in a figure. 1... Bus interface section (BIF), 2... Address memory section (AM), 3... Address memory address control section (AMAC), 4... Data memory section (D
M), 5...Data memory address control unit (DMAC
>, 6...Memory control unit (MCC), 7...CPU
Bus, 8... Main control circuit (CPU), 9... Main memory circuit (MEM).

Claims (1)

[Claims] first means connected to a common bus to which at least a main control circuit and a main memory circuit are connected and storing address information to be output to the bus; and address information to be output stored in the first means. The second one that indicates the address location.
and a third means for inputting and outputting data to and from the bus.
a fourth means for instructing the third means to specify a storage address position of data to be input/output; and a fourth means for transmitting a direct memory access control signal and a read/write control signal to the bus; Said first, second,
and fifth means for controlling the third and fourth means.