JPS6337418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a simple memory data transfer device in a microcomputer or minicomputer system.

[Prior art]

Conventionally, it was the first device to realize this type of function.
I got what is shown in the figure. In the figure, 1 is the central processing unit (CPU), 2 is the main memory, and 3 is the CPU 1.
and main memory 2; 4 is a CPU bus for controlling the input/output devices of the system; 5 is a CPU bus for controlling input/output devices of the system;
is DMA (direct memory access)
Controller 6 is a device controller that controls the magnetic disk device 8 and flexible disk device 9, and 7 is a DMA bus that connects the DMA controller 5 and device controller 6.

Next, the operation shown in FIG. 1 will be explained below.
Now, consider the case where the contents of the magnetic disk device 8 are transferred to the main memory 2. Control information is given from the CPU 1 via the CPU bus 4 to the device controller 6 that controls the magnetic disk device 8. The device controller 6 moves to control the device based on the control information, and when the preparation for transferring the control information is completed, the device controller 6 transfers the control information to the DMA controller 5.
It is output via the DMA bus 7 to make a DMA request. Therefore, if the DMA controller 5 can accept the request, it sequentially transfers data with the device controller 6 in DMA mode, and executes the data transfer onto the main memory 2 via the internal bus 3. Then, when the transfer of all data is completed, or when an error occurs and it becomes impossible to retry, the device controller 6 transfers the detailed status to the main memory 2, and then the device controller 6 sends a completion signal to the CPU 1. Output via CPU bus 4. CPU
1 receives this completion signal, executes the termination process, and moves on to the next step.

Note that the DMA controller 5 can perform DMA with a plurality of device controllers 6 at the same time. In other words, the DMA bus 7 receives its own DMA request from each device controller 6 and responds independently.
It is now possible to process by time division and multiplexing control.

Since the conventional simple memory data transfer device is configured as described above, in order to transfer data from a device controller to another device controller, it is necessary to transfer data once to the main memory 2. Even though the transfer speed of DMA is high, the overall transfer speed is slow, so DMA cannot be used for high-speed data transfer. Also, DMA requests and responses between the DMA controller 5 and device controller 6 are one-to-one.
This method increased the number of signal lines for the DMA bus, and the polling method had the drawbacks of wasted time.

[Summary of the invention]

This invention was made to eliminate the above-mentioned drawbacks of the conventional controller, and it concentrates the functions of the DMA controller in one place, allowing transfer multiplexing and
The objective is to provide a simple memory data transfer device that performs arbitrary multiplexed DMA transfers between memory boards on the DMA bus at a speed comparable to that of conventional devices by centrally controlling the DMA bus. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals.
2-port memory common to CPU bus 4 and DMA bus 7; 15 is a flexible disk controller; shared memory is internal and can be accessed from CPU bus 4 and DMA bus 7; 9 is a flexible disk controller; This is a flexible disk device connected to a disk controller 15.

Next, the operation shown in FIG. 2 will be explained. for example,
An example of copying the contents of the flexible disk device 9 to the magnetic disk device 8 will be shown. First, control parameters are output from the CPU 1 to the flexible disk controller 15 via the CPU bus 4. The flexible disk controller 15 starts its control by this operation, reads out the contents of the flexible disk device 9, sets it in the shared memory inside the flexible disk controller 15, and outputs a completion signal to the CPU 1 when the setting is completed. Subsequently, the CPU 1 outputs a DMA request to the DMA controller 5 to transfer the contents of the flexible disk device 9 to the magnetic disk device 8 of the magnetic disk controller 17 via the flexible disk controller 15. The DMA controller 5 executes this DMA request via the DMA bus 7 and outputs a completion signal to the CPU 1 upon completion. Therefore, the CPU 1 continues to output a magnetic disk write command to the magnetic disk controller 17 via the CPU bus 4, and finally outputs a magnetic disk write command to the magnetic disk controller 17.
1 receives a write completion signal from the magnetic disk controller 17 and the copying is completed. During the copying operation, for example, from memory 14 to memory 14'
When a memory-to-memory DMA transfer is required, the CPU
1, it is sufficient to add a DMA request to the DMA controller 5. Priority control and error handling related to DMA multiplexing are all performed within the DMA controller 5, and are communicated through the internal bus 3.
Controlled arbitrarily from CPU1.

The DMA controller 5 uses the DMA bus 7 to execute two sequences, ie, reading data from the memory 14 and writing data to the memory 14', a specified number of times.

Here, since the memories 14 and 14' are 2-port memory type, when a memory access conflict from CPU bus 4 and DMA bus 7 occurs, priority is taken into consideration even if no switching control signal is given from CPU 1. Since automatic arbitration is performed, even while a DMA transfer is being executed, the CPU 1 can use the memory used in the transfer.

In the above example, for the 2-port memories 14 and 14', the CPU bus 4 and DMA bus 7
Since addressing is possible independently from each bus, by setting aside a wide address space for the DMA bus 7, data in the memory space that cannot be accessed by the CPU bus 4 can be switched using high-speed transfer by the DMA controller 5. This enables high-speed processing.

〔Effect of the invention〕

As described above, according to the present invention, the DMA controller has a bus configuration that allows it to perform highly functional operations under the intensive monitoring of the CPU, so there are no restrictions on the operation of the system CPU, all of which are controlled by the system CPU. It is possible to transfer high-speed data independently between the memory on the CPU bus and the DMA bus in parallel with the CPU operation, without giving rise to high-speed data processing in the total system.

Furthermore, by concentrating the functions, it is possible to reduce the cost of hardware, which has the effect of providing a simple memory data transfer device that is cheaper than conventional products.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing a conventional DMA mechanism, and FIG. 2 is a system block diagram of a simple memory data transfer device showing an embodiment of the present invention. 1...Central processing unit (CPU), 2...Main memory, 3...Internal bus, 4...CPU bus, 5...
DMA controller, 6...Device controller, 7...DMA bus, 8...Magnetic disk device, 9...Flexible disk device, 14,1
4'...Memory, 15...Flexible disk controller, 17...Magnetic disk controller.

Claims (1)

[Claims] 1. A CPU and a DMA controller connected by an internal bus, a CPU bus and a DMA bus that the CPU and DMA controller can control independently of each other, and a plurality of two-port memories shared by the CPU bus and the DMA bus. A simple memory data transfer device equipped with multiple disk controllers.