JPS61131152A - Dma buffer control system - Google Patents

Abstract

PURPOSE:To attain data transfer between each IO controller and a DMA buffer into through a main storage device by using a direct memory access (DMA) memory part as a DMA buffer and providing it to a common bus together with a DMA controller. CONSTITUTION:In transferring a data from the input/output controllers IOC 12-14 to the DMA buffer 21, the control information such as transfer start address and byte number is set to the DMA controller by a CPU 11. Then a data is transferred via a common bus 16 under the control of the controller 15 to the DMA buffer 21 from the IOC 12-14. In transferring the data from the buffer 21 to the IOC 12-14, the reverse operation as above is executed and the data is transferred. The CPU 11 is released at data transfer between the IOC 12-14 and the buffer 12, and a main storage device MEM 20 is connected to the CPU 11 not through the common bus 16, then the data is processed between the CPU 11 and the MEM 20 in parallel with the data transfer processing.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a DMA buffer control method in which data is transferred from each input/output device by DMA (direct memory access) control using a DMA buffer. for,
The present invention relates to a DMA buffer control method in which a DMA buffer is connected together with a DMA control device to a common bus, and the DMA buffer is used in place of a main memory to transfer data between input/output control devices by DMA control.

[Conventional technology]

Conventionally, in order to transfer data between the input/output device (hereinafter referred to as 0) and the main memory at high speed, the main memory is directly accessed without going through the central processing unit (hereinafter referred to as CPU). It is well known that a DMA method is used to transfer data between computers.

FIG. 3 shows a conventional DMA control method.

A CPU, a main memory device (hereinafter referred to as MEM), an input/output control device (hereinafter referred to as ROC), and a DMA control device are interconnected via a common bus. Each l0Co~I
IOo to ICh are connected to OC2, respectively. A data buffer is allocated to a portion of the MEM to store data to be transferred to and from the IOC.

In this configuration, the CPU sets control information such as the transfer start address of the MEM and the number of transfer words in a register in the DMA control device using an initialization program. When this set is completed, the CPU activates the DMA control device.

For example, when data is to be transferred from rho to r02, l0Co notifies the DMA control device of a data transfer request to MEM.

Upon receiving this notification, the DMA control device instructs the CPU to
Issue a request signal. When this DMA request is accepted by the CPU, the DMA control device
The data of o is transferred to the address area in the MEM and written. When writing of a predetermined number of data is completed, the DMA control device sends an interrupt signal to the CPU and ends the transfer operation.

When the CPU receives this interrupt signal, the CPU performs IO in the MEM.
Knowing that writing of the data in o is completed, performs an operation to transfer this data to IO2.

That is, the CPU uses IO stored in the MEM.

The transfer start address and number of transferred words for the data are D.
It is set in a register in the MA control device to activate the DMA control device.

When the DMA@control device receives this activation, it sends DMA to the CPU.
A request signal is issued, and when the request signal is accepted, the data of IOo in MEM is transferred to IO2 via 10C2. When the transfer of a predetermined number of data is completed, the DMA control device sends an interrupt signal to the CPU and ends the transfer operation.

Data transfer using the conventional DMA method is performed as described above, so while data 1 is being transferred using DMA, the CPU cannot access the MEM, and conversely, the data transfer between the CPU and the MEM is While the data is being processed, the DMA control device is configured to be unable to access the MEM and transfer roc data. This is a phenomenon common to various conventional DMA systems.

[Problem that the invention seeks to solve]

In the conventional DMA system, as described above, a part of the MEM is allocated as a data buffer for the IOC. Therefore, MEM access when reading and executing instructions performed by the CPU, and MEM access during IOC data transfer
There was a conflict in access, and while one party was accessing the MEM, the other party was unable to access the MEM. As a result, for the CPU, the instruction execution time increases, I
The problem with OC is that it causes a decrease in data transfer speed.

[Means for solving problems]

The present invention solves the above-mentioned problems in the conventional DMA system, enables parallel processing of CPU MEM access and IOC data transfer operation, and improves roc data transfer rate and C
This provides a DMA buffer control method that improves both the instruction execution speed of the PU, and as a means for this purpose, multiple input/output control devices are connected to the central processing unit and the DMA buffer via a common bus.
Data that connects to the MA control device, transfers control information between the central processing unit, DMA control device, and each input/output control device, and transfers data between each input/output control device via a common bus by DMA control. In the transfer method, the main memory device is connected to the central processing unit, and the DMA buffer that stores the data transferred from each input/output control device or the data transferred to each input/output control device is connected to a common bus separately from the main memory device. The bus is connected to at least each input/output control device and DMA control device via a common bus, and data is transferred between each input/output control device and the DMA buffer via a common bus without going through the main storage device. be.

[Operation] When data is transferred from the input/output control device to the DMA buffer, the central processing unit sends control information such as the transfer start address and the number of bytes to the DMA control device, and then the data is transferred under the control of the DMA control device. D from input/output control device
Data is transferred to the MA buffer via a common bus.

Also, when transferring data from the DMA buffer to the input/output controller, control information such as the transfer start address and number of bytes is set in the DMA controller by the central processing unit, and then the DMA buffer is transferred under the control of the DMA controller. Data is transferred from the input/output controller to the input/output controller via a common bus. During data transfer between the input/output control unit and the DMA buffer, the central processing unit is released and the main memory is connected to the central processing unit without going through the common bus. Data processing is performed between the processing device and the main storage device.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of one embodiment of the present invention, and FIG. 2 is a detailed explanatory diagram of a DMA control device used in the same embodiment.

In Figure 1, 11 is the CPU, 12 to 14 are l0Go
= IOC2, 15 are DMA control devices, common bus 16
are interconnected through. 17-19 are l0C
o 12”'l0C2L IO connected to 4 respectively
It is. The number of IOCs and ■0s is not limited to three sets, and a plurality of other sets can be arranged; however, in the following explanation, the case of three sets will be explained as an example.

20 is a MEM, but in the present invention, it does not have a data buffer area for storing data of each 10C,
Connected to CPUI 1. 21 is a DMA buffer,
It is connected to at least the DMA control device 15 and each of the 10 CIs 2 to 14 via a common bus 16.

In FIG. 2, the portion surrounded by a chain line is the DMA control device 15. Reference numeral 22 constituting the DMA control device 15 is a priority circuit, which receives each data transfer request signal DMA RQ sent from l0Co to IOC1.
The one with the highest priority is selected from among DMA RQ 1 to DMA RQ 2. CPU, DMA
S Lo , DM ASLl , and DMA5L2 are CPU, 10Co , l0CI , and l0C , respectively.
This is a DMA select signal for 2. 23-26 are
CPUI 1 for the DMA buffer 21, respectively;
l0Co l7.

CPU address register (CPADR2) where the transfer start address of 10C+18 and 10C219 is written.
3), Data memory address register (DMA D R
o 24 to DMA D R226). 27-29
are DMA buffer 21 and ■○Co17 to l0, respectively.
The number of data transferred between C219s is set in bytes. Data memory byte count register (
DMBCRo27 to DMBCR229). 30～
32 subtracts "1" from the byte count numbers of DMBCRo 27 to DMBCR 229. In other words, “=1”
is an adder. 33 is an interrupt generator, DMBCR.

When the byte count number of any one of 27 to DMBCR 229 becomes "O", an interrupt signal INT is generated. 3
4 to 40 are AND circuits, and 41 and 42 are NAND AND circuits or OR circuits. In addition, DMADR and DMBCR
Although the case of 3 each is shown as 311, the present invention
As mentioned above, this is not limited to the case of il.

Next, the operations shown in FIGS. 1 and 2 will be explained, taking as an example the case where data is transferred from IOo to fo2.

The CPU II controls the DMADR624 to DMA of the DMA control device 15 via the common bus 6 according to the initial program.
l0Co 1 for DMA buffer 21 in DRa26
Write the transfer start address of 1 to l0C219 and DM
I OGo 17 to BCRo 27 to DMBCR229
~I Set the number of data to be transferred from the OC 219 in bytes.

The DMA buffer 21 can also be accessed by the CPUI 1, in which case an address is written to the CPADR 23. However, CPUI 1 is D
The operation of accessing the MA buffer 21 starts from IOo (0
2, and a detailed explanation thereof will be omitted. Each DMADR and D
When writing of each control information to the MBCR is completed, each IOC is instructed to start data transfer.

When receiving the instruction to start data transfer from the CPU II, the 10Cos 12 to 10Cs 214 send respective data transfer request signals DMARQo = D M to the DMA control device 15 in response to data transfer requests from the Ioos 17 to 10219 connected thereto. r RQ 2
Send out.

The priority circuit 22 of the DMA control device 15 receives data transfer request signals DMARQ o to DMARQ from each IOC.
If there is a conflict in 2, the highest priority t+)I O
It selects the data transfer request signal DMARQ from C and responds with a DMA select signal DMA5L.

Assume now that DMARQo from l0Co is selected and DMARQo corresponding to it is output. C.P.
When the DMA buffer 21 is not accessed by the UI 1, DMA5Lo is sent to 1oco12 via the AND circuit 34.

10Co12 is DMA5Lo from the DMA control device 21.
When the data is received, the data is transferred in byte units to the DMA buffer 21 via the common bus 16. Every time one byte of data from l0Co12 to l0o17 is transferred to the DMA buffer 21, the address of DMADRo24 is @1.
The value of DMBCRo27 is subtracted by 1'' by the adder 30 to indicate the number of remaining data bytes. The address of DMADRo24 becomes the address of DMA buffer 21 via AND circuit 38 and OR circuit 43.

When the data transfer of the number of bytes specified by CPUII to l0Co12 is completed, that is, DMBCRo
When the content of 27 becomes O'', the interrupt generation circuit 33 generates an interrupt signal INT to cause an interrupt to the CPUI 1.

The CPU 11 sends data 1 of l0Co12 to the DMA buffer 21 using this interrupt signal INT.
When it is detected that the transfer is completed, the DMA buffer 21
The process moves on to transfer the data of l0o17 stored in 10219 via l0C214.

CPU II stores l0o stored in DMA buffer 2I.
After writing the start address of data No. 17 to DMA5Lo 26 and setting the number of bytes of the data to DM B CR2, it notifies IOC2 that there is a data transfer. When l0C2 detects that IO2 is ready to accept data, it sends D M A RQ 2 to D
It is sent to the MA control device 21.

The priority circuit 22 of the DMA control device 15 controls the DMA
When RQ 2 is selected, D M A S L 2 becomes 1
002 and stored in the DMA buffer 21
The data of o17 is transferred to IO219 via roc214. Every time 1 byte of 0θ 17 data is transferred from the DMA buffer 21, the address of DMADR 226 is incremented by 1 to indicate the address of the next 1 byte of data to be transferred, and the value of DMBCR 229 is The adder 32 subtracts by "1" to indicate the number of remaining data bytes. The address of DMBCR 226 becomes the address of DMA buffer 21 via AND circuit 40 and OR circuit 43.

When the data transfer of the number of bytes specified by CPUII to l0C2 is completed, that is, DMBCR229
When the content becomes "O", the interrupt generation circuit 33 generates an interrupt signal INT to cause an interrupt to CFULL.

When the CPU II detects that the data transfer from the DMA buffer 21 to 0.19 is completed by this interrupt signal INT, it shifts to the next data processing requested by the CPU II itself or the IOC.

The above explanation is an explanation of the operation when transferring data from [Oo to IO2;
Data transfer between PUI 1 and each 10 is performed in the same manner.

Furthermore, the CPUI 1 can read from or write to the DMA buffer 21. In that case, CPAD
An address is set in R23 and the CPU 5L is set to "1" to access the DMA buffer 21.

In this way, in the present invention, the data transfer performed between each IOC and the DMA buffer is controlled by the DMA control device 15. Therefore, CPU1l has each ■OC
After starting the ME, it is released from data transfer control, so in parallel with the data transfer processing performed between
Data processing can be performed with M20.

〔Effect of the invention〕

As explained above, according to the present invention, the DMA memory part that was conventionally provided in the MEM is provided as a DMA buffer on the common bus side together with the DMA control device, so that data transfer processing between each IOC and each IOC and DM
Data transfer between the A buffers can be performed without going through the MEM. Therefore, it is possible to perform data processing between the CPU (!:MEM) in parallel with these data transfer processes, so the instruction execution speed of the CPU and each I/O
Both can improve the data transfer speed of the OC.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of a DMA control device used in the same embodiment, and FIG. 3 is an explanatory diagram of a conventional DMA control system.

Claims (1)

[Claims] A plurality of input/output control devices are connected to a central processing unit and a DMA control device via a common bus, and control information is transferred between the central processing unit, DMA control device, and each input/output control device, and each input/output control device In a data transfer method in which data is transferred via a common bus under DMA control, the main storage device is connected to the central processing unit, and the data transferred from each input/output control device or transferred to each input/output control device is A DMA buffer that stores data is connected to at least each input/output control device and DMA control device via a common bus separately from the main memory, and the DMA buffer is connected to each input/output control device and the DMA buffer without going through the main memory. A DMA buffer control method characterized in that data is transferred via a common bus.