JPH0690711B2 - Memory access control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial field of application Conventional techniques and problems to be solved by the invention Means for solving problems Problems Working Examples Effects of the invention [Outline] At least one To a few memory devices, one to a plurality of first memory access requesting device groups, and one to a plurality of second memory access requesting device groups, the first memory access requesting device Storage control provided with a priority control circuit for prioritizing a memory access request from a group and a memory access request from the second memory access requesting device group and accessing the storage device by a plurality of data buses Regarding the memory access control method in a memory system composed of devices, the number of read data buses and write data buses between the storage control devices For the purpose of reducing the number of memory access request devices, the read data bus and the write data bus consisting of the plurality of lines between the storage device and the storage control device are divided into the number of types of memory access request device groups, and the first memory access request is made. Memory access from the device (CPU) group is performed using a specific data bus of the divided data bus, and memory access from the second memory access requesting device (VU) group is divided into the divided data buses. It is configured to use all the data buses of the data buses.

[Industrial application field]

The present invention provides at least one or a plurality of storage devices,
One to a plurality of first memory access request device groups,
A memory access request from the first memory access requesting device group and a memory access request from the second memory access requesting device group. The present invention relates to a memory access control method in memory access configured by a storage control device having a priority control circuit that takes priority and accesses the storage device by a plurality of data buses.

Usually, in a vector processing unit or the like, a large amount of vector data is transferred from the main storage unit (MSU) to a vector register (VR) or the like in order to perform vector operation, and the data from the vector register (VR) is transferred. The data is sequentially read out, the operation is performed by the operation pipeline, the obtained data is written to the vector register (VR), the written data is transferred to the main storage unit (MSU), and the writing is performed.

These operations are generally executed by three stages of vector load instruction, vector operation instruction, and vector store instruction.

In addition to this, there is load / store access by a scalar instruction of the central processing unit (CPU).

Thus, at least the storage control unit (MCU) and the main storage unit (MS) that process memory access requests from the vector processing unit (VU) that processes vector data and the scalar data processing device that processes scalar data.
It was necessary to connect a load / store data bus for the vector processing unit (VU) and a load / store data bus from the central processing unit (CPU) to the U).

However, in a data processing system including such a storage control unit (MCU), the usage rate of the data bus between the storage control unit (MCU) and the main storage unit (MSU) depends on the amount of flowing data. , Vector processing unit (VU)
It is expected that the construction of an efficient memory access control system will be realized, considering that the above is overwhelmingly large.

[Problems to be solved by conventional technology and invention]

FIG. 3 is a diagram for explaining a conventional memory access control system, in which (a) shows a case of a load system and (b) shows a case of a store system.

First, in FIG. 3 (a), a central processing unit (CPU) 3
The vector instruction sent from the vector processing unit (VU) 2 is recognized by the vector instruction control unit 22 as a vector operation instruction or a vector access instruction (vector load instruction). If the vector access instruction is sent to an operation pipeline (not shown), the recognized vector load instruction is sent to the load access instruction processing unit (A or B) 21a.

For example, in the load access instruction processing unit (A) 21a, when the vector load instruction is received, the vector address generation unit (A) 210 uses the above-mentioned start address, distance, and vector length to Request address signals are sequentially sent to the MSU plan orientation control unit 44 of the storage control unit (MCU) 4 while adding the distance to the head address.

The MSU priority control unit 44 activates each main storage device (hereinafter referred to as MSU) 1 by taking bank busy (depending on the priority between elements, etc.), priority with other access devices (for example, CPU), etc. . {Refer to MSU activation signal} In each MSU (0, 1) 1, the MSU priority control unit 44
Based on the address information from, the desired module and bank are activated and the data of MSU (0,1) 1 is read.

The read data is subjected to an error code check (ECC), for example, by an error correction circuit, then passes through a read data bus, a storage control unit (MCU) 4, and a vector processing unit (VU). 2 is input to the load align circuit 212a of the load access instruction processing unit (A) 21a, and the alignment is performed so that it can be sent to the desired vector register (VR0,1)) 23 according to the element number of the data and the memory address. Done.

The aligned data is temporarily stored in the load data buffer 21.
It is held by 3a, for example, when 2 elements are aligned,
Writing to the vector register (VR0,1) 23 is performed simultaneously.

The gate signal to the load align circuit 212a is supplied to the MSU priority control unit 44 of the storage control unit (MCU) 4.
Is generated by the vector load instruction control unit (A) 211a based on the alignment information sent from the MSU1 at the timing of the data sent.

Next, referring to FIG. 3 (b), a schematic operation of a conventional vector store instruction will be described.

Regarding the operation of the vector store instruction, the same operation as the operation of the vector load instruction is performed by the vector address generation unit (A or B) 210 and the MSU priority control unit 44 of the storage control unit (MCU) 4.

That is, the MSU (0,1) 1 is booted, and at the same time, its priority information is transferred to the vector store instruction control unit (A).
The data is input to the 211b, and the store data is stored in advance from the stored store data buffer 213b in the store align circuit 212b.
, Then the corresponding MSU (0, 1) via the write data bus via the storage controller (MCU) 4.
Send to 1.

Further, in FIGS. 3 (a) and 3 (b), the central processing unit (CP
The instruction fetch and data fetch from U) 3 are performed in the same way as the memory access from the vector processing unit (VU0,1) 2, and the request address signal is sent to the MSU priority controller 44 of the storage controller (MCU) 4. MSU (0,
1) The data read from 1 is passed through a dedicated data bus, the storage control unit (MCU) 4, and the central processing unit (C
PU) 2 load / store data bus.

Since the central processing unit (CPU) 3 generally has a buffer storage 31, a series of blocks to be stored in the buffer storage 31 is read for the memory access.

Then, once in the storage control unit (MCU) 4, MSU (0,1) 1
The data read from is put into a buffer register so that the data that the central processing unit (CPU) 1 needs most can be sent first, and the data bus width with the central processing unit (CPU) 3 is narrowed. (For example, 16-byte width and 8-byte width).

In FIG. 3 (b), generally, a central processing unit (CPU)
Also in the case of storing from No. 3, the processing of the store operation is reduced as much as possible by transferring in block units as much as possible.

For this reason, buffering is performed in the storage control unit (MCU) 4, and the store access process is performed on the MSU 1 at the stage when the blocks are prepared.

Therefore, in the conventional memory access control system, a dedicated write data bus / read data bus is set up for memory access from the central processing unit (CPU) 3 with low access frequency, and the hardware amount (connection cable There was a problem that there were many lines.

In view of the above conventional drawbacks, the present invention has at least one or a plurality of storage devices and one or a plurality of first memory access requesting device groups {for example, a central processing unit (CPU)}.
And one or a plurality of second memory access requesting device groups {for example, vector processing unit (VU0,1)}, the memory access request from the central processing unit (CPU), and the vector processing unit. (VU) group memory access requests are prioritized, and a memory processing system comprising a storage controller having an access priority control circuit with a plurality of data buses in the storage device has a central processing unit (CPU). ) Is less frequently accessed than other processors, for example, the frequency of memory access from the vector processing unit, and the data bus from the storage controller to the storage is used efficiently. An object of the present invention is to provide a memory access control method that reduces the amount of hardware.

[Means for solving problems]

FIG. 1 is a principle diagram of a memory access control system of the present invention, and the above problems are solved by the memory access control system having the following configuration.

At least one or a plurality of storage devices 1, one or a plurality of first memory access requesting device groups 3 and one or a plurality of second memory access requesting device groups 2 are provided. The memory access request from the first memory access requesting device group 3 and the memory access request from the second memory access requesting device group 2 are prioritized, and a plurality of data buses are provided in the storage device 1. Storage controller 4 having bus priority control circuit 44a for access
In the memory system, the read data bus and the write data bus consisting of the plurality of lines between the storage device 1 and the storage control device 4 are divided into the number of types of memory access requesting device groups, and the first memory The memory access from the access requesting device 3 group is performed using a specific data bus of the divided data bus, and the memory access from the second memory access requesting device 2 group is performed by the divided data bus. It is configured to use all the data buses of.

[Action]

That is, according to the present invention, the storage control unit (MCU) connects the data bus between the main storage units (MS0 to n) to the memory access requesting unit, for example, the central processing unit (CPU) and the vector processing unit (VU0,1). ) And the central processing unit (C
PU) and the access pipeline of the vector processing unit (VU0,1) can be used only by the read data bus and write data bus (shown by the dotted line) and the access pipeline of the vector processing unit (VU0,1) It is classified into a read data bus and a write data bus (shown by solid lines) that can be used.

When the vector compression / expansion conversion instruction disclosed in the “vector instruction processing method” filed separately by the applicant of the present application is executed, the frequency of occurrence of the instruction is higher than that of a general vector load / store instruction. Therefore, only one (A) of the two access pipelines in the vector processing unit (VU0,1) is operated and only the data bus indicated by the solid line is used. Similarly, for a memory access request from a central processing unit (CPU) having a low frequency of occurrence, only the data bus indicated by a dotted line different from the above is used.

Therefore, the data bus dedicated to the central processing unit (CPU) can be deleted without significantly lowering the overall throughput of the data processing system. Further, by using the data bus used by the vector compression / expansion instruction and the data bus used by the central processing unit (CPU) separately, priority control becomes easy.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a principle diagram of the memory access control system of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. The MSU priority in FIG. 1 and FIG. The data bus (solid line) extending between the control unit 44 and the storage control unit (MCU) 4 and the main storage unit (MSU0, 1, ...) 1 and the (dotted line) implement the present invention. It is a necessary means. The same reference numerals indicate the same objects throughout the drawings.

The memory access control system of the present invention will be described below with reference to FIGS. Since the store system has the same connection configuration as the load system, in order to make the drawing easier to see,
A part of the connecting line is omitted.

Generally, as the data processing system becomes faster and larger, for example, it is required to shorten the access time to the main memory unit (MSU) 1. Therefore, the central processing unit (CPU) 3
A buffer memory 31 having a capacity as large as possible is provided therein, and data processing (load system / store system process) in the central processing unit (CPU) 1 is performed with the buffer memory 31.

Further, in the vector processing, in order to perform a series of vector processing, it is required to execute a vector load instruction, a vector operation instruction, and a vector store instruction at high speed. For this reason, measures are taken to reduce the access time of vector access instructions, such as the vector processing unit (VU0,
1) Align processing unit 212 in 2 and load / store data buffer 213, data processing unit for access instructions such as vector register (VR0, 1) 23, and storage control unit (MCU) 4
The load data circuit 41 and the store data circuit 42 therein are made to coexist in the vector processing unit (VU0, 1) 2 to shorten the access time. (See FIGS. 2 and 3) In such a data processing system, in order to further increase the speed, a plurality of vector processing units (VU0,1) 2 are connected in parallel as shown in FIG. In addition to the above, the data transfer path 11 is provided in the main storage device (MSU0, 1, ...) 1 to efficiently perform vector compression / expansion conversion. Instruction processing method ”.

The memory access in such a data processing system is roughly divided into the following: (1) Central processing unit (CPU) 3 with low access frequency
(2) Memory access by the above-mentioned vector compression / expansion conversion instruction, which occurs less frequently than the normal vector load / store access (It is originally a data transfer instruction between vector processing units (VU)) However, in order to reduce the amount of hardware, the data bus with the main memory unit (MSU0,1 ...) 1 and the data transfer path 11 in the main memory unit (MSU0,1 ...) 1 are used. Memory access for execution} (3) It can be classified into the memory access by the normal vector load / store instruction.

Therefore, as shown in the principle diagram of FIG. 1 and FIG.
In the present invention, when the access pipeline A25 is used for vector compression / expansion instructions, normal vector load / store access from the access pipeline B26 is performed by the main memory (MSU0,1) 1-vector processing unit. It is necessary to control by the MSU priority control unit 44 so that the solid line part in the data bus between (VU0,1) 2 is not used, and as shown in FIG. 1, the bus priority in the MSU priority control unit 44 is prioritized. The vector load / store instruction control section indicates that the access pipeline A25 is being executed by the vector compression / expansion instruction in the order control circuit 44a.
Control is performed by notifying from A211.

The above control can also be managed by the vector command control unit 22, for example. That is, when the vector compression / expansion instruction is transmitted to the access pipeline A25, the access pipeline B26 is controlled not to operate. Further, under the transmission condition for the access pipeline B26, the access pipeline A25 is controlled to transmit because the vector compression / expansion instruction is not operating.

By performing such memory access control, in the normal vector load / store access, two elements of the vector data are shown by a solid line and a dotted line by using the access pipeline A25 and the access pipeline B26, respectively. By transferring data through two load / store data buses, data transfer of a total of four elements is performed between one vector processing unit (VU0) 2 and the main memory (MSU0, 1, ...) 1. be able to.

Further, as described above, in the memory access when executing the vector compression / expansion instruction disclosed in the “Vector instruction processing method” filed separately by the applicant of the present application, only the data bus indicated by the solid line is used. Use main memory (MS
Through the data transfer path 11 in U0,1) 1, one vector processing unit (VU0) 2 can simultaneously perform compression / expansion conversion of two vector elements.

That is, one of the elements is the vector processing unit (VU0)
2 to the data transfer path 11 of the main memory (MSU0) 1 is used, and in other elements, the same vector processing unit (VU0) 2 to the data transfer path 1 of the main memory (MSU1) 1
By using 1, it is possible to execute compression / expansion conversion processing for two elements.

In the memory access from the central processing unit (CPU) 3, high-speed data processing is performed with the data block stored in the buffer memory 31 in the central processing unit (CPU) 3, When the data block required in the buffer memory 31 does not exist (that is, in the case of a mishit), a block fetch request is output to the main memory device (MSU0, 1, ...) 1 and the above-mentioned vector processing unit. As indicated by the dotted line, the vector processing unit (VU0,1) 2 is rarely used, paying attention to the fact that the frequency of memory access is low compared to the memory access to the vector data from (VU0,1) 2. The move-in process is performed by using only the data bus.
Of course, at this time, the bus priority control circuit 44a in the MSU priority control unit 44 in the storage control unit (MCU) 4 may recognize the condition that the bus is not used in the vector load / store instruction. is necessary.

As described above, according to the present invention, the memory access requests from a plurality of devices are given priority to the data bus by the MSU priority control unit in the storage control unit (MCU), and the main storage units (MSU0, 1, ...) Are given priority. Paying attention to the difference in the frequency of occurrence of memory access requests from each device in the method of performing memory access between the devices, divide the data bus into at least the number of device types, and It is characterized in that a usable data bus is selectively allocated according to the type of memory access request to perform memory access.

〔The invention's effect〕

As described above in detail, the memory access control method according to the present invention includes at least one or more storage devices, one or more first memory access request device groups, and one or more storage devices. A second memory access requesting device group, and prioritizes the memory access request from the first memory access requesting device group and the memory access request from the second memory access requesting device group. ,
In a memory access control system in a memory system including a storage control device having a priority control circuit for accessing the storage device by a plurality of data buses, read data composed of a plurality of storage devices between the storage device and the storage control device. The bus and the write data bus are divided into the number of types of memory access requesting device group, and the memory access from the first memory access requesting device (CPU) is
The specific data bus of the divided data bus is used, and the memory access from the second memory access requesting unit (VU) group is performed by using all the data buses of the divided data bus. Since it is configured to do so, there is an effect that the data bus dedicated to the central processing unit (CPU) can be deleted without significantly reducing the overall throughput of the data processing system. Further, by separating the data bus used by the vector compression / expansion instruction from the data bus used by the central processing unit (CPU), priority control becomes easy.

[Brief description of drawings]

 FIG. 1 is a principle diagram of a memory access control system of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram explaining a conventional memory access control system. . In the drawing, 1 is a main memory (MSU0,1, ...), 11 is a data transfer path, 2 is a vector processing unit (VU0,1), 21a is a load access instruction processing unit (A, B), and 21b is store access. Instruction processing unit (A, B), 210 is vector address generation unit (A, B), 211 is vector load / store instruction control unit, 211a is vector load instruction control unit (A, B), 211b is vector store instruction control Part (A, B), 212a is a load align circuit, 212b is a store align circuit, 213a is a load data buffer, 213b is a store data buffer, 22 is a vector instruction control unit, 23 is a vector register (VR0,1), is a write Data bus, read data bus, request address signal, MSU activation signal, CPU dedicated data bus, load / store data bus (solid line), load / store data bus (dotted line), 25 access pattern Pline A, 26 is an access pipeline B, 3 is a central processing unit (CPU), 31 is a buffer memory, 4 is a memory controller (MCU), 44 is an MSU priority control unit, 44a is a bus priority control circuit, respectively. Show.

Claims (1)

[Claims] 1. At least one or a plurality of storage devices (1), a group of one or a plurality of first memory access requesting devices (3), and one or a plurality of second memory accesses. A requesting device (2) group, and a priority order of the memory access request from the first memory access requesting device (3) group and the memory access request from the second memory access requesting device (2) group And a plurality of data buses (,
) Bus priority control circuit (44)
In a memory system comprising a storage control device (4) including a), a memory access is made to the read data bus and the write data bus consisting of the plurality of storage devices (1) and (4). Dividing into the number of types of requesting device group, the memory access from the first memory access requesting device (3) group is performed using a specific data bus () of the divided data bus, The memory access control method is characterized in that memory access from the memory access requesting device (2) group is controlled by using all the data buses (,) of the divided data buses.