JPS5941215B2 - Main memory write control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main storage write control system, and in particular, a port section that temporarily holds an access request for writing to the main storage device, and a a shift register that receives various control information including address information and write data from the port section and holds the control information during an access cycle;
The present invention relates to a main memory write control method that performs partial writing by merging data read from a main memory and write data output from the shift register.

In a system having a high-speed buffer storage device inside a processing device, one of the following two control methods is adopted. (i) Store-through method (Ii) Swap method Each method has its advantages and disadvantages, and it is a difficult problem to choose which method to use, but in general, store and through methods are often used.

The disadvantage of the store-through method is that writing to memory is required not only to the buffer storage device but also to the main memory, so in the case of continuous write requests, access to the main memory becomes a bottleneck. As a result, processing speed is subject to restrictions.

In order to solve this problem, the following various measures have been taken. (1) The main memory is divided into 8-byte [B] boundary units (referred to as interleaf units), and access control is performed independently in interleaf units.

In other words, even if there are consecutive write requests, access will not be granted if the interleaf is different.

However, generally, the data length handled when a processing device executes an instruction is 4 bytes [B] (referred to as WORD).

) unit, there is a high possibility that successive processing results will be stored twice for one and the same interleaf. In order to deal with this, the unit of interleaf should be set to 4 [B], but this would require a significant increase in hardware and would be difficult to implement.

(2) In 8 [B] interleaf control like (1),
Check the data. Bit (ERRORCORR
Since the ECTCODE (called ECTCODE (ECC)) is held for 8[B], when writing data less than 8[B] (called PARTIALSTORE [partial write]), first [F] -8[B] is stored. ] Requires a very long sequence of reading data, 2 merging, 3 ECC generation (GENERATE), and writing.

Therefore, in order to reduce the probability of partial writing, if the write area on main storage is in buffer storage,
It is merged with the data from the buffer storage device to create a full write (FULL STORE) as 8 [B] data.

Further, during full writing (FULLSTORE), there is no need to read from the proxy storage device, and the process is completed only by generating and writing check bits.

However, in this (2) countermeasure, (a) considering the remarkable increase in hardware, if there is no write area in the buffer storage device, the conventional method will be lost; Since it is an area, there is a high probability that it does not exist.

(b) Multi. In the system, if two or more processing devices issue write requests to the same -8 [B] at the same time, the subsequent write will overwrite the previous write with old data (0VERWRITE). Since there is a possibility, it is multi-purpose. It has drawbacks such as being extremely difficult to implement in a system.

8[B] For continuous write processing in an interleaf control system, if each write request exceeds the 8[B] boundary, by increasing the number of interleafs to a certain extent, most of the write processing is not completed. It can be executed without any problems.

However, if write requests within the -8[B] boundary occur consecutively, subsequent write processing will have to wait for a very long time.

Furthermore, considering that most instructions are processed in units of 4 [B] called words, this answer rate is quite high.

The present invention aims to solve the above-mentioned problems. Therefore, the present invention provides a port unit that temporarily holds an access request for writing to the main storage device, and a port unit that temporarily holds an access request and access address information when the access request is accepted. and a shift register that receives various control information including write data from the port section and holds the control information during an access cycle, and transfers the data read from the main memory device and the write data output from the shift register. In a main memory write control method that performs partial writing by merging, means is provided for comparing the access address information output from the shift register with the access address information held in the port section, and When the comparison means detects that write requests are continuously occurring to the area of the same access unit, the following write request data is merged with the previous write processing data being executed. The feature is that the process is completed with a single write operation.

Hereinafter, the present invention will be explained with reference to the drawings.

First, in order to facilitate understanding of the present invention, we will begin with four commonly used multiprocessors. A conventional example of a main memory control unit (MCU) in a system will be described.

FIG. 1 shows a conventional example of a main memory control device, and in the figure, 1-
1 to 1-2 are central processing units (CPU), 2-1 to 2-2
is a channel processing unit (CHP), 3-1 to 3-2 are main storage units (MSU), 4 is a main storage control unit (MCU), 5
-1 to 5-4 are port units (PORT) that hold access requests from the processing device, control information, addresses and data; 6 is a priority control circuit; 7 is a selection circuit;
9 is a storage control section, and 9 is a shift register, which stores data in the port section. 10 is a check bit generation circuit, 11 is an address conversion circuit, 12 is a merge circuit, and 13 is a key. Registers, 14 is a read data register, 15 is a write data register, 16 is an address register, 17
18 is an error check circuit, 18 is a key information output circuit, and 19 is an error check circuit.
is a data output circuit.

The operation of FIG. 1 is as follows. Access requests from the processing devices 1 and 2 are once held in the port unit 5.

One of the access requests to the port section 5 is selected by the priority control circuit 6, and if the corresponding storage unit (LS) is not busy (BUSY), access to the main storage device 3 is started and the necessary Data, addresses, and control information are stored in the shift blocks that make up the pipeline. Set in register 9. All necessary information is held in the shift register 9 and used to control subsequent operations.

Therefore, at the time when access to the main storage device 3 is started, the selected port section 5 becomes vacant and can accept the next access from the processing device.

In addition, if the next access is to a different storage unit (LS) and the storage unit (LS) is not busy, the access can be started without having to wait one by one.

In the case of partial writing (PARTIAL STORE), access to the main storage device 3 is started from the 8[B] fetch in the same area.

In the final stage of the shift register 9 pipeline,
Read data from main storage device 3 is loaded into read data register 14 .

Therefore, the error check circuit 17 for the read data
It checks the data, merges it with the write data held in the final stage of the pipeline, generates a check code for the merged data, and stores it in the main memory again. Activate access.
Similarly, address and control information is stored in the shift blocks that make up the pipeline. Set in register 9.

Next, FIG. 2 shows the configuration of a main memory feeding control device according to an embodiment of the present invention.

In FIG. 2, the same numbers as in FIG. 1 indicate the same components, and the newly added component is a comparator circuit 20.

Furthermore, the merge circuit 12 has some additional functions. Comparison circuit 20 is a loop from the pipeline. Back. The address is compared with the address of the port section 5, and based on the comparison result, the merging circuit 12 merges not only the data on the pipeline but also the data of the port section 5 at the same time.

Partial writing already mentioned (PARTIAL STORE)
In the operation, the loop in the final stage of the pipeline. Back. The address is compared with the address of the port unit 5 corresponding to the processing device that activated the partial write being executed.

Then, when the following conditions are met (comparison match)・(store request)=゛1゜゛The data read from the main storage device 3 is merged with the data of the final stage of the pipeline, and then the data of the port section 5 is added. After merging the data, a check code is generated, and the store data is stored in the main memory 3 again. Activate access. At that point, the next write request existing in the port section 5 also activates the pipeline, and the port section 5 becomes vacant. Therefore,
The port section 5 can accept the following access from the processing device, and the processing device stores most of the data in words (
Considering that the next access is also a write request, it can be considered that it is to a different storage unit (LS).
It is possible to continue processing in sequence without having to wait at the port unit 5. FIG. 3 is a peripheral circuit diagram of the comparison circuit 20. In FIG. 3, 12 is a merge circuit, 20 is a comparison circuit, 30 to 32 are selection circuits, 33 is a decode circuit,
34-35 are AND gates, 36 is Latch, PORTS
EL is a port selection signal, LBSEL is a loop. Back selection signal, PORTNO is the port number, LBNO is the loop. Back number, PORTAI) DR is the address from the port section, PORTDATA is the data from the port section, LOOPBACKADDR is the loop from the pipeline. Back. Address,LOOPBACKCMDSTO
RE is the store request signal from the pipeline, PORTS
TORE is a store request signal from the port section, LOOPB
ACKDATA is a loop from the pipeline. Back.
The data, ECCDATA, is read data from the main memory.

In FIG. 3, when a port part number is selected by the selection circuit 32, the decoding circuit 33 and the selection circuit 30,
31, the address and data from the corresponding port section are obtained, and the address from the port section is passed through the loop.31. Back. compared to the address.

When a comparison match output is obtained from the comparison circuit 20, and the access request from the port section is a store request, and the output from the pipeline indicates a store request, the output signal of the AND gate 34 is output, and the latch 36 Turn on. As a result, the AND gate 35 is opened, and the data from the port section is input to the merge circuit 12, where it is merged with the output data from the pipeline and the read data from the main storage device. In addition, in FIG. 3, the selection circuits 30 to 32 and the decoding circuit 33 can be used in combination with existing circuits.

Next, FIG. 4 is an example of a time chart when two consecutive stores are merged.

In Figure 4, MSREQ/MSOP/MSADDR
/MSDATA is the period when the CPU is sending a request/operation/address/data.
ACK is the PO during the period when the acceptance signal is received from the MCU.
RTREQ/PORTOP/PORTADDR/POR
TDATA is the period when the port section holds the request/operation/address/data.
RTACK is the period when the acceptance signal is sent to the CPU.
RIORITY & CMECK is a period in which the priority control circuit 6 shown in FIG. This is the period during which access to the first unit begins.

The pipeline consisting of shift registers shown in Figure 2 is 0.
It consists of 14 stages of ~13, and during the first fetch cycle, address comparison is performed in the 12th stage, and the next 13th
Merging is done in stages. The merged data is written to the main memory by the store cycle, which is the second access. In addition, in FIG. 4, the store for the next -8 bytes [B] activated during the period indicated by a square can be merged. As described above, according to the present invention,
It detects that write requests are occurring continuously for the same access unit of the main storage device, merges the subsequent write request data at the same time, and completes the write in one operation. (1) Processing result in 4 bytes [B]
(2) Since the busy time of one storage unit (LS) is reduced, subsequent processing by this processing device and other processing is greatly improved. When used in combination with (3) an increase in the number of interleaves, the above-mentioned store. It has excellent effects such as almost eliminating the drawbacks of the through method.

[Brief explanation of the drawing]

Fig. 1 is a conventional example of a main memory control device, Fig. 2 is a configuration of a main memory control device according to an embodiment of the present invention, Fig. 3 is a peripheral circuit diagram of a comparison circuit, and Fig. 4 is a continuous two-way This is an example of a time chart when stores are merged. In the figure, 1-1 to 1-2 are central processing units, 3-1 to 3-2
4 is a main storage device, 4 is a main storage control device, 5-1 to 5-4 are port sections, 6 is a priority control circuit, 7 is a selection circuit, 8 is a storage control section, 9 is a shift register, and 10 is a check bit. 12 is a merging circuit, 14 is a read data register, 15 is a write data register, 16 is an address register, 17 is an error check circuit, and 20 is a comparison circuit.

Claims (1)

[Claims] 1. A port section temporarily holds an access request for writing to the main storage device, and when an access request is accepted, receives access address information and various control information including write data from the port section, and performs an access cycle. In a main memory write control method that has a shift register that holds the control information, and performs partial writing by merging data read from the main memory and write data output from the shift register, the shift register A means is provided to compare the access address information output from the port section with the access address information held in the port section, and write requests are continuously generated to the same access unit area on the main storage device. is detected by the comparison means, the subsequent write request data is merged with the previous write processing data being executed, thereby completing the processing in one write operation. .