JPS62285180A - Vector processor - Google Patents

Abstract

PURPOSE:To successively process the part only and to guarantee a correct counting result when the same indirect address value exists by suppressing the reading processing of a list vector when possibility P that the data on the main storage device of a list vector element are re-written by the result of the vector calculation which is executed at present exists. CONSTITUTION:Vector data (VD) are successively read from a main storage device 1 in accordance with the address shown by an address register (AR) 14 by a load instruction and accumulated through writing data registers (WR) 2-5 to vector registers (VR) 6-9. The VD of VRs 6-9 is read and sent through a reading register 10 to an AR 15 and a list vector control unit 19. The unit 19 decides whether possibility P that the data on a main storage device designated by the address are re-written by the result of the vector calculation which is executed at present exists. When the deciding result shows that the possibility exists, the unit 19 closes a gate 20, suppresses the load of the VD from the main storage device 1 and when the possibility does exist, the next processing is proceeded.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention provides a method for reading vector data expressed in a list vector format from a main storage device for vector operations;
The present invention relates to a vector processor that performs arithmetic processing and storage in a main memory at high speed.

[Conventional technology]

Vector processors have been devised for high-speed processing such as large matrix calculations that frequently appear in scientific and technical calculations.

Many of the vector processors include
78, there is a list vector processing function as detailed below. In other words, high-speed reading/reading of vector data with a list structure specified by indirect addresses is possible.
Writing is possible. By using this list vector processing function, it is possible to perform vector processing at high speed as shown in the following Fortran sentence.

Do 10 I=1. N D(A(I))=B(A(I))+C 10C0NTINTJE In other words, add the constant C to the vector element B(A(I)) indicated by the indirect address vector element A(I),
The calculation result is stored in vector element D (A(I)) indicated by indirect address vector element A(I). In this manner, the vector processor can perform operations on vector data specified by the indirect address vector at high speed using vector processing techniques.

However, conventional vector processors cannot perform vector processing as shown in the following Fortran statement.

Do to I=1. N R(A(I))=Fl(A(T))+C10C0NTI
NUE In other words, a constant C is added to the vector element B (A (I)) indicated by the indirect address vector element A (I), and the result of the operation is added to the vector element R (A (I)).
Vector processing could not be performed for storing data in . This is due to the defined reference relationship of vector element F3 (A(I)). That is, in the above example, vector element B(A
(I)) as data, a certain operation is performed and the result is used to update the vector element R(A(I)), but in vector processing, the vector element B(A(T))
Before the update of
(A(J)) is read, so if the contents of A(1) and A(J) are equal, the result of the operation performed on B(A(T)) is R(A(J)). The problem is that it is not reflected in the calculations performed on ). For this reason, the above processing cannot be vector processed and must be executed sequentially, so high-speed processing cannot be expected.

The above-described processing, that is, the processing of performing calculations on a list vector and storing the results in the list vector, is essential in, for example, hidden surface removal processing in computer graphics. In hidden surface removal processing such as the Z-buffer method, the depth values of each pixel are compared, and the depth values on the main storage device are changed based on the comparison results. Pixel positions are given by list vectors. When vector processing is performed on a plurality of polygons, list vector processing may be performed on the same pixel, that is, the same address, and this is exactly the vector processing at issue in this patent.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, in the process of performing an operation on a list vector and storing the operation result in the list vector,
If the same indirect address value exists, this is not considered, and the next list vector element is read without waiting for the previous processing to finish and the list vector value to be updated, so the result of the previous operation is There were reports that the results were not reflected in the later calculation data, resulting in incorrect results being obtained.

In view of the above-mentioned problems, the present invention provides a method that allows correct results to be obtained even when the same indirect address value exists in the process of performing an operation on a list vector and storing the result of the operation in the list vector. Its purpose is to provide a vector processor.

[Means for solving problems]

The above object is to provide a means for determining whether or not there is a possibility P that the data on the main memory of a list vector element will be rewritten by the result of the currently executed vector operation in an operation on a list vector, and to This is achieved by determining the possibility P for the list vector element before reading it from main memory, and inhibiting reading of the list vector element while the possibility P exists.

[Effect]

In list vector processing, the list vector control unit holds addresses in main memory that have a probability P of being altered by the currently executed vector operation. Before reading a primary list vector element, the list vector control unit determines the possibility P for the address of the list vector.

If the possibility P exists, the list vector control unit suppresses the read processing of the list vector. Therefore, if the same indirect address value exists, only that part is processed sequentially, so correct calculation results are guaranteed.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIG.

FIG. 1 shows the configuration of a portion of a vector processor system that performs vector operations that is related to the present invention. In the figure, 1 is the main memory, 2 to 5 are the write data registers of the respective vector registers, 6 to 9 are the vector registers, 10 to 13 are the data registers written from the vector registers, and 14 to 7 are the write data registers of the respective vector registers. This is an address register for accessing vector data.

18 is an arithmetic unit, which performs a predetermined arithmetic operation.

The list vector control unit 19 is a characteristic feature of the present invention, and its details will be described later.

20 is a gate. In the figure, inputs to vector write registers 2 to 5, vector read registers 10 to
The output from address register 13 and the input to address registers 14 to 17 are each fixed, but in reality, each is set by a selector (not shown).

That is, the inputs of write registers 2 to 5 are sent to the main memory ff by a selector (not shown) in accordance with the specified program.
It is connected to l1 or the output of the arithmetic unit 18. Further, the outputs of the read registers 10 to 13 are connected to an address register, a list vector control unit, an S7 processor, or a main storage device by a selector (not shown) in accordance with a designated program.

Next, the operation will be explained in detail. -For example, the following Fo
Consider an operation as expressed in the rtran program.

Do 10 T=1. , N B(A(T))=B(A(I))+C 10C0NTINU E First, vector data is read out from the main storage device 1 according to the address indicated by the address register 14 by a load instruction, and the vector data is read out from the main storage device 1 via the write data register 2. Ti is multiplied in register 6. The address register 14 is incremented by 1 each time reading of vector data is completed. As described above, vector data A (L ~
N) are sequentially read out and stored in the vector register 6.

Next, the vector data in the vector register 6 is read out and sent to the address register 15 and list vector control unit 19 via the read register 10. The control unit 19 regards the input data as an address in the main memory.

The list vector control unit 19 determines whether there is a possibility P that the data on the main memory specified by the address will be rewritten by the result of the vector operation currently being executed.

The internal configuration of the list vector control unit 19 will be described in detail later. The operation of the list vector control unit is as follows depending on the presence or absence of the possibility P.

(1) When there is a possibility P If the possibility P exists, the list vector control unit 19 sends a signal to the gate 20, closes the gate 20, and transfers the vector data from the main memory 1 to the vector register 7. Prevent loading.

When the vector operation being executed progresses and the possibility P disappears, a signal is sent to the gate 20 to open the gate.

(2) When there is no possibility P When there is no possibility P, the list vector control unit 19 sets the possibility P corresponding to the address to be valid and proceeds to the next process.

When the gate 20 is open, vector data is read from the main memory device 1 according to the address indicated by the address register 15 by the next load instruction, and is stored in the vector register 7 via the write data register 3.

Do as above.

Main memory i! 21 to list vector data 11 (A
(1 to N)) is read out and stored in the vector register 7.

Furthermore, the vector data in the vector register 7 is sent to the arithmetic unit 18 via the read register 11, where a pre-specified arithmetic operation (addition of constant C in the above program example) is performed, and the result of the arithmetic operation is sent to the write register 5. The signal is then sent to the vector register 9. As described above, vector data B(A(1-N))+C are accumulated in the vector register 9.

Vector data A (L to N) is stored in the vector register 8 through the same processing as in the vector register 6.

The vector data in the vector register 8 is sent to the address register 17 via the read register 12. Vector data in vector register 9 is read register 1
3, and is written into the main memory device 1 according to the address indicated in the address register core. As described above, the vector operation result B(A(,1-N))+C is written to the main memory. Next, the data in the address register 17 is transferred to the list vector control unit 19, and the list vector control unit 19 determines the possibility that the data in the main memory specified by the address will be rewritten by the vector operation currently being executed. change to nothing.

In the manner described above, the vector calculation indicated by the program is realized.

FIG. 2 shows a simple time chart of this embodiment. For simplicity, read requests, transfers from registers to arithmetic units, etc. are omitted. Reading of vector data A (1 to N) from the main memory device 1 is performed every cycle in order from element 1 to element N, as shown in the figure.

Additionally, indirect address vector data is added in the next cycle.
For (A(1-N)), the list vector control unit 19 examines the possibility P of rewriting data for the address. If the possibility P exists, reading of n (A (1 to N)) is inhibited until the possibility P becomes null. The figure shows the case where A (2) = A (4). Main storage device 1 of n(A (4))
It is necessary to wait until the operation on R(A (2)) is completed before reading from. This means that if the possibility P exists, R(A (i)) until the possibility P becomes null.
This is achieved by inhibiting the reading of .

In the figure, processing for elements 1 to 3, that is, reading of A(1 to 3), reading of B(A(1 to 3)),
As for addition and writing of operation results, since there is no possibility P mentioned above, they should be executed in order every cycle. Regarding element 4, since the possibility P exists, reading of B(A(4)) is waited until the processing of B(A(2)) is completed.
After completing the process of (2)), r((A (4~N)
), addition, and storage of the operation results are executed in order every cycle.

As above, if identical indirect address values exist,
The data is not pipelined, but processed sequentially. However, vector operations are performed unless identical indirect address values exist. Therefore, if there are almost no identical indirect address values, pipeline processing is possible for most of the data, and speeds comparable to ordinary vector processors can be obtained. If there are many identical indirect address values, sequential processing increases, but even in the worst case, the speed of a scalar processor that performs sequential processing is guaranteed.

FIG. 3 is a conceptual diagram of a vector processor system using a conventional method. The difference with the present invention is that the list vector control unit 19 is not present, and the operation is almost the same as the vector processor system of the present invention shown in FIG. In the example in Figure 3, the list vector B(A(
1 to n)) from the main memory 1, it is not determined whether or not there is a possibility that the cough value will be rewritten by the result of the vector operation currently being executed. For this reason, for example, A (2
) = A (4), the operation result for B(A (2)) is B
It is not reflected in the calculation of (A (4) ), and the correct result cannot be obtained. FIG. 4 shows a simple time chart of a Vegtor processor according to the conventional method. In the same figure, reading of R(A (4)) is B(A (2)
') is performed before the writing of the operation result is completed. For this reason, correct results cannot be obtained.

Next, one embodiment of the list vector control unit 19 will be described in detail with reference to the flowchart of FIG. The unit is read from read register 10 in Figure 1 to address A.
The action begins by taking (i). In Figure 5 (a), first enter address A (i).
01), and then assigns the result f(A(i)) of the operation ftt at the address A(i) to the variable Key. Operation f
This will be explained in detail later.

Next, using the variable Key, draw a conflict table that holds whether the address is in use or not (103), and if it is not in use, the gate 2
0, opens the gate 20 (104), makes the table busy, and ends the process (105).
In step 3, if it is busy, a signal is sent to the gate 20, the gate 20 is closed (1, 06), and the process returns to step 103.

When the output A(j) of the address register 17 in FIG. 1 is input to the list vector control unit 19, an interrupt is generated and an interrupt operation is started. Figure 5(b)
, first input the address A(j) (201),
Next, the operation f is performed on the address A (j), and the operation result f
Assign (A (j)) to K ey (202)
. Next, set the Key element of the table to no
+ is set to busy and the process ends (203). Note that the table Table.

is a one-dimensional array with M elements, and all elements are no+
It is assumed that it is initialized to busy.

If the operation f applied to the address value A (i) is an identity transformation, the number M of elements of the conflict table Tabla will be the number of all addresses that can be accessed.

If L is a relatively small number, it is sufficient to set f as an identity transformation and provide a conflict table for all addresses that can be referenced. If the total number of addresses that can be accessed is very large, it is disadvantageous in terms of hardware to have a conflict table for all addresses. At this time, it is effective to reduce the number of addresses by the operation f. For example, r:
In the case of 2z0, if we consider an operation in which only the lower 8 bits of f are valid, then 256 elements in the conflict table is sufficient.

As explained above, according to the present invention, in the process of performing an operation on a list vector and storing the result of the operation in the list vector, if the same indirect address value exists, the previous process is terminated. Since the list vector element corresponding to the same indirect address is read after the value of the list vector is updated, a correct operation result can be obtained even if the same indirect address value exists. Further, the only new processing required to realize the present invention is the calculation of function C and table lookup, which can be realized at high speed by performing mask processing on function f. Therefore, if there are no identical indirect address values,
Although the conventional method can be used, even when the method of the present invention is used, there is almost no decrease in speed, and high-speed vector processing is possible.

In the worst case, that is, when all indirect address values are the same, processing becomes sequential, but the speed of a scalar processor that performs sequential processing is guaranteed.

The effects of the present invention are most effective when the same indirect address value rarely exists. Conventional vector processors cannot obtain correct results in the above-mentioned cases, and require sequential processing, making it impossible to achieve high-speed processing. However, even in the above case, according to the present invention, there is almost no delay in reading list vectors, and a speed equivalent to that of a normal vector processor can be obtained.

In this embodiment, a case has been described in which constants are added to list vector elements and the operation results are stored in the list vector, but it goes without saying that vector processing can be performed similarly for multiple operations with other vector data.

In this embodiment, reading of a list vector element from the main memory is inhibited due to a conflict between the list vector elements, and if there is no conflict after that, the list vector element is stored in the main memory, and immediately after that, the list vector element is stored in the main memory. The element will be read from main memory.

As a modification of this embodiment, if the output of the read register 13 is input to the write register 3 via a selector, there is no need to refer to the main memory, and even higher speeds can be realized.

[Effects of the Invention] As described above, according to the present invention, in the process of performing an operation on a list vector and storing the result of the operation in the list vector, vector processing is performed even when the same indirect address exists. This has the effect of improving processing speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart of the embodiment, Fig. 3 is a block diagram of an embodiment according to the prior art, Fig. 4 is a tie 11 chart, and Fig. 5 (a),
(b) is a flowchart showing the processing of the list vector control unit.

Claims (1)

[Scope of Claims] 1. In a vector processor system having a plurality of vector data, means for reading vector data 2 for calculation from a main storage device based on indirect address vector data 1; In a vector processor having means for performing a pre-specified operation and means for writing the result of the operation into the main storage device based on the indirect address vector data 1, for a given address value, the indirect address vector data 1;
Before reading the calculation vector data 2 from the main storage based on the above, check whether there is a possibility P that the data on the main storage to which the address value is specified will be rewritten by the result of the vector calculation currently being executed. (1) If the possibility P does not exist, read the calculation vector data 2 from the main memory based on the address value, and (2) If the possibility P exists, the possibility P is
A vector processor characterized in that reading of the vector data 2 from a main memory is inhibited until the vector data 2 is exhausted. 2. The vector processor according to item 1 has a conflict table that holds the possibilities P for all addresses that can be referenced, and the possibility P is determined by table lookup of the conflict table. vector processor. 3. The vector processor of item 1 has an arithmetic unit that performs an operation f on an address value, performs the operation f on a given address a, and uses the operation result f(a) to resolve the conflict. Referring to the table, the possibility P
A vector processor characterized by determining.