JPS5836434B2 - Batshua Memory Souch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the performance of a buffer memory of an information processing device.

2. Description of the Related Art In recent years, the amount of information processed by information processing apparatuses has become increasingly large, and the processing contents have become more complex.

In order to meet these demands, a high-speed and large-capacity storage device is required, but increasing the capacity and increasing the speed are contradictory.

As a solution to this problem, a small capacity and high speed buffer memory is provided within the central processing unit.

This has made it possible to effectively provide a storage device with large capacity and high speed.

However, in order to enable even faster information processing, 1
A so-called pipeline control method, which processes several instructions in parallel at a time, has come to be used.

In this method, at the same time, the operand read command is read,
It is necessary to be able to store data.

It is necessary to improve the throughput of buffer memory.

An example is introduced in which two-way interleaving of buffer memory is adopted as a method for improving the throughput of buffer memory.

The present invention further improves the buffer memory and makes it possible to speed up instruction reading.

The number of bytes of instructions and data that a central processing unit reads from a storage device at one time is usually made to match the data width of the storage device.

Therefore, when instruction execution starts or the flow of instruction execution changes, the first instruction address is
An instruction is read, but depending on the address boundary of the instruction, the entire instruction code to be executed may not necessarily be contained in the first instruction read.

If all instruction codes cannot be read, execution of the instruction cannot be started and must wait until reading of the next instruction is completed.

For example, if the data width of a storage device is 8 bytes and the instruction code is 4 bytes, if the instruction address is on a 6-byte boundary, the instruction cannot be executed until the next 8 bytes are read. be.

Furthermore, if there is no 8-byte boundary, after executing one instruction, it is still necessary to wait until the next 8 bytes are read.

In programs for information processing devices, branch instructions that change the flow of instructions are frequently used, and the above-mentioned performance degradation is the key to high-speed information processing.

Even if the flow of instruction processing described above is not sequential,
In order to be able to read instructions at high speed and utilize the ability of pipeline control quickly, two or more instructions that can always be executed at a time must be stored in the instruction buffer (
InstructionBuffer; IBR)
What is necessary is to provide a device to capture the data.

For this purpose, the device of the present invention is configured to read out data twice the normal data width at a time during instruction reading, and to be able to take it into the IBR.

That is, by utilizing the features of the device of the present invention, which includes a buffer memory in which the memory section of the buffer memory is composed of two banks, and each bank can be read simultaneously, when an instruction exists in the buffer memory, both banks are read out simultaneously. By simultaneously reading consecutive instructions from the IBR and importing them into the IBR, two or more executable instructions can exist in the IBR, and the instructions can be processed one after another without interruption.

FIG. 1 is a block diagram of an embodiment of the present invention, showing the buffer memories 15, 16, IBRs 17, 18, and the flow of addresses for reading instructions.

This buffer memory device employs a set-association/shutive system with a data width of 8 bytes, a buffer memory capacity of 16 kbytes, 128 columns, and 4 rows.

As is clear from the address format described below, the buffer memory device stores data (commands) held in a main memory (not shown) as a copy, with each block consisting of 32 bytes.

The data width of each buffer memory IJ15, IJ16 is 8 bytes, and addresses are alternately assigned.

That is, addresses 0 to 7, 16 to 23 are assigned to the buffer memory 15, addresses 8 to 15, and 23 to 31 are assigned to the buffer memory 16 within the block.

When a program starts executing in a processing unit, an instruction address is converted from a logical address to a real address, and the TL
B (Translation lookaside B
instruction address register 3 (IAR e, Instruction A) through path 20
ddressRegister) and is sent to the buffer memory through the path 21,
The instruction read request is assumed to be 111.

At this time, the 27th address in IAR3. The 28 bits are tested in control circuit 4 to determine whether they can be read from both banks of buffer memory at once.

If possible, HS. IF (High Speed In
Fetching) signal is “1”
becomes.

No if this is not possible or if reading instructions sequentially
R. I F (Normal Instruction
n Fetching) signal becomes lI''.

The control circuit 4 at the time of instruction reading is shown in FIG. 2 and will be described later.

When the instruction read is accepted in the buffer memory, the path 21
is set in register 5, and access to the buffer memory is started.

This device has a data width of 8 bytes and a buffer memory capacity of 16
Since it uses a set associative method with KB, 128 columns, and 4 rows, the buffer memory directory 7 is accessed via the decoder 6 using the 20 to 26 bits of the address, and the output data is , comparison circuit 8
The 8th to 19th bits of register 5 are compared to check whether the desired data is in the buffer memory.

The comparison result is encoded by the encoder 9 and becomes the upper two bits of the address in the memory section of the buffer memory.

In the case of normal instruction read, the 28th bit of the address is referred to, and if this bit is "ol", the even bank 15 is accessed, and if this bit is "I", the odd bank 16 is accessed.

Also HS. In the case of IF, both banks are accessed simultaneously.

Therefore, H.S. In the case of IF, the 2 bits obtained from the row encoder 9 and the 7 bits of the column address are stored in the read address registers 11 and 12 of the buffer memory.
The 27th bit of the address is set at the same time.

However, the 27th bit of the address is 0 and the 28th bit is 1.
In this case, the address requesting reading is an address in the block from 8 to 15 and points to the buffer memory 16 in an odd bank, and the 27th bit is set to 1 in the read address register 11 of the buffer memory 15 in an even bank. , in the even bank buffer memory 15, 8 bytes 16 to 23 are read out at addresses within the block.

The outputs of the memory sections 15 and 16 of the buffer memory are respectively set in the instruction buffer IBR 17 and 18, and execution of the instruction is started.

19 is an instruction register. Similarly, when reading the branch destination instruction with a branch instruction, HS. IF is specified, and execution of the branch destination instruction after a successful branch can be started earlier.

FIG. 2 shows a control signal circuit obtained from an address when reading an instruction.

If the 27th and 28th bits of the address are both 111, the intra-block address points to 23 to 31, and this is the last 8 bytes of the buffer memory block, so H
S. Since it is impossible to read consecutive instructions from both banks using the IF, the HS. Do not set IF to '1l' N
OR. The IF is set to 111.

H.S. When the IF is set to "11", when an instruction read request is accepted, the next instruction read address needs to be incremented by +16, a +16 signal is set, and the adder circuit 1 in FIG. 1 increments the address by +16.

Also NOR. In the case of IF, the +8 signal becomes 1, and the instruction read address is increased by +8 in the adder circuit 1 of FIG.

Furthermore, if the 27th bit of the address is O and the 28th bit is 1, the least significant bit of the buffer memory address of the even bank must be set to 1.
The t(28) bit signal becomes 1 and the OR circuit 10 in FIG.
is being entered.

The flow of instruction processing is disturbed by branch instructions, interrupt processing, system state change instructions, etc., and the frequency of these occurrences is about 30 or more, although it depends on the program.

When this disturbance in instruction processing occurs, the execution of instructions is started faster than in conventional devices, thus making it possible to improve processing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of this device, and FIG. 2 is a block diagram of the first device.
FIG. 4 is a block diagram showing details of the circuit 4 in the figure. 3... Instruction address register, 4... Control circuit, 7
...Buffer memory directories 15 and 16
...Buffer memory, 17 and 18...Instruction buffer.

Claims (1)

[Claims] 1. The memory section of the buffer memory that stores data in units of blocks consisting of multiple bytes is composed of double-variable banks, and in a buffer memory device that can read and write from each bank simultaneously and independently, data is read from each bank according to an address that requests reading. It has a control circuit that determines whether it is possible to read instructions at consecutive addresses at the same time, and if possible, controls the reading of consecutive addresses from each bank, and depending on whether it is possible, the next instruction A buffer memory device characterized by controlling an added value for reading.