JPS6049347B2 - Memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access method, and particularly to control of advance reading of instructions.

The process of reading an instruction, decoding it, executing it, and then reading the next instruction is called sequential read control, whereas the process of predicting the instructions that will be executed in the future and reading them in advance, Preliminary read control is a method for proceeding some processing in parallel with the current instruction processing. Preliminary reading of an instruction includes reading the next instruction in parallel with the execution when the address of the next instruction is determined and the main memory is free, even if the execution of the next instruction has not finished. Even if the address of the instruction is undetermined, one or several instructions ahead may be predicted and read out to the high-speed buffer.

Furthermore, if frequently used words are stored in a high-speed buffer, access time can be shortened, and processing speed can be expected to be improved by sharing this with advance control. Conventionally, processing devices not equipped with high-speed buffers are rarely expected to have very high processing performance, and therefore advance control has not been forced.

In general, pre-reading of an instruction is not performed during the execution of the previous instruction, but multiple instructions are read at once and buffered before instruction execution, and read from this buffer as necessary.
A method of fetching and executing instructions one by one is used.

Conventionally, as shown in FIG. 1, a main memory device 2 divided into banks M1 to Mn is connected to a processing device 1, and an instruction to be executed next is stored during execution of a certain data cycle. A method has been proposed in which a plurality of data are read out in advance (see Japanese Patent Publication No. 50-9657).

In this case, the processing device 1 is provided with an instruction stack 10 for holding prefetch instructions and a data stack 11 for holding data processed by write instructions, and the n memory banks have addresses that are interleaved with each other. has been done. In this way, it is considered desirable to increase the instruction buffer (instruction stack) in order to speed up processing, but in programs with many branch instructions, this increases the overhead and reduces efficiency. It has the disadvantage of becoming.

Furthermore, since adding a buffer memory to a medium-speed computer is not preferable from a price/performance ratio, it is necessary to improve the processing capacity without providing a buffer memory.

When pre-reading an instruction using a high-speed buffer, for example, as shown in FIG. It takes two machine cycles to execute the address conversion Δ2 of the next instruction in parallel with the execution E1 of the previous instruction.
, instruction reading, and instruction execution E2.

However, if a high-speed buffer is not provided, the access time for reading memory cannot be shortened, so the second
As shown in FIG.
Normally, each of the machine cycles and instruction executions El and E2 takes about four machine ● cycles.

Therefore, when pre-reading the next instruction in parallel while the previous instruction is being executed, it takes time to read the next instruction, which may cause the reading of the previous operand to have to wait. .

Since such inconvenience cannot be allowed to occur, it is not easy to perform advance control in a processing device that does not have a high-speed buffer. SUMMARY OF THE INVENTION In order to solve such problems, it is an object of the present invention to enable pre-reading of instructions without affecting the currently executing instructions in a processing device that does not have a buffer memory, thereby improving the price and performance of the processing device. We provide a memory access method that can improve the ratio! There are many things.

The memory access method of the present invention is applicable to operand reading or operand writing during instruction execution in a data processing device that sequentially reads and executes instructions from a storage device interleaved in a plurality of banks.
When an access request is issued, using this request as a trigger, if the banks are different, a read request for the preceding instruction is issued with a delay of one machine cycle, and if the banks are the same, the read request for the preceding instruction is invalidated. There are certain characteristics.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of a data processing device to which the present invention is applied, and FIGS. 4 and 5 are time charts of the memory access method according to the present invention, respectively.

Central processing unit (hereinafter referred to as CPU) 1 and main memory unit (hereinafter referred to as MS)
) 2 are connected via the access control line 3, address line 4, and data line 5, and the memory access control unit 11, memory address register unit 12, and data register unit 13 in the CPU1 are connected to the access control line 3, address line 4, and data line 5. 3. The address lines are connected to the data lines 5, respectively.

SMS2 has a 4-way configuration, with each bank having 26
29 can operate independently via bank control sections 22 to 25.

In the CPU1, the instruction control unit 14 sequentially reads out the instructions stored in the MS2, decodes and executes the instructions, and executes the commands (control unit 15).
The execution control unit 15 executes the command.

The execution of the instruction involves sequentially opening and closing the gates of each section according to the instruction code, and also opening and closing the MS2 gates specified in the address section.
The operand is read from the address and calculations are performed. In these operations, requests for accessing the MS 2 are for reading instructions from the instruction control section 14 and for reading or writing data from the execution control section 15 .

Normally, the instruction control section 14 and the execution control section 15 do not operate at the same time, but in the present invention, in order to reduce processing time, as shown in FIG. After l, during the period during which instruction execution E1 is being performed, preparations for execution of the next instruction are made in parallel, that is, address translation of the instruction, reading of the instruction, and decoding of the read instruction, so that the instruction can be executed. Make it.

Such advance control is performed by the instruction control unit 14, and after execution preparation is completed, the execution operation is performed by the execution control unit 15. In this case, as shown in FIG. 4, if execution preparation AL2 for the next instruction is started at the same time as execution E1 of the previous instruction is started, if the next instruction and data happen to be stored in the same bank, If a read request for the next instruction is issued first, the read of the previous data may be delayed. Therefore, in the present invention, as shown in FIG. 5, after the start of execution of the previous instruction, a read request for the next instruction is made to a different bank, triggered by an operand read request.

Note that one data read request during execution E1 of the previous instruction in FIG. D2 indicates that the data is being read, and D3 indicates that the read data is being taken in. In addition, in FIG. 5, 0P1 is a read request for the next instruction;
P2 indicates that the instruction is being read, and 0P3 indicates that the instruction is being fetched.

The data read request D1 in FIG. 5 is a memory access request issued from the execution control unit 15 and
5 indicates the period until the application is accepted.

At this time, the memory address is sent to the memory address register section 12. The MS 2 receives a memory access request at the common control unit 21 and at the same time receives a memory address sent from the memory address register unit 12. Further, the bank selection bit that is part of this memory address selects the bank in question, and if the bank is vacant, control is transferred to one of the bank control units 22-25. For example, assume that bank 0 is selected. D2 in FIG. 5 indicates the time during which the memory section 26 of bank O is being accessed. The read data acquisition D3 in FIG.
The data read from the memory section 26 is transferred to the bank O via the control section 22, the common control section 21, and the data line 5.
Data of PUl ◆ Indicates the time until it is stored in the register section 13. Preparation for execution of the next instruction occurs during the execution of the previous instruction.
Immediately after the bank containing the data to be read is determined, that is, triggered by an operand read request,
This is done by issuing a request for pre-reading an instruction to a bank different from the bank in which the data is stored.

In this way, it is possible to perform advance reading of an instruction overlapping the operand read period, which shortens the instruction execution period and eliminates the inconvenience of having to wait for the previous operand read due to the read of a later instruction. It doesn't happen. Of course,
When the bank from which the previous operand is read is the same as the bank from which the next instruction is read, the read operation of the next instruction may be made to wait.

The instruction read request 0P1 in FIG. 5 is a memory access request issued from the instruction control unit 14,
25.

At this time, the command address is sent to the memory address section 12, and the MS2 performs the same operation as the data read request. However, the selected bank is a bank different from bank O for data reading, for example, bank 1. Fifth
The instruction read column 0P2 in the figure indicates the time during which the memory section 27 of bank 1 is being accessed. In the instruction fetch 0P3 in FIG. 5, the instruction read from the memory section 27 enters the data register section 13 of the CPU1 via the control section 23 of bank 1, the common control section 21, and the data line 5, and the instruction is controlled. The time required to enter the instruction buffer of the unit 14 is shown.

A memory for reading operands from the execution control unit 15.
A sequence in which an access request is sent and accepted by the bank control units 22 to 25, and a memory access request for advance reading of the next instruction is sent from the instruction control unit 14 is a microprogram. This can be easily achieved by Although FIG. 5 shows a case where the preceding instruction reading is performed in parallel with the data reading, the preceding instruction reading is not limited to data reading. It is possible.

Further, in the embodiment, the number of memory access requests is limited to one, but it is also possible to accept a plurality of memory access requests at the same time.

As described above, according to the present invention, when reading a preceding instruction in duplicate with other memory accesses, processing time can be shortened without adversely affecting the execution of the previous instruction; High-speed buffer 7A C without storage device
If applied to reading a preceding instruction in a PU, the price/performance ratio can be improved.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the conventional advance control system;
FIG. 3 is a block diagram of a data processing device to which the present invention is applied, and FIGS. 4 and 5 each illustrate a memory access method according to the present invention. FIG. 1: CPU12: Main storage device, 3: Access control unit, 4
: Address line, 5: Data line, 11: Memory access control section, 12: Memory address ● register section, 13:
Data Register section, 14: Instruction control section, 15: Execution control section, 21: Common control section, 22 to 25: Bank control section,
26-29: Bank●Memory section.

Claims (1)

[Claims] 1 From storage interleaved in multiple banks,
In a data processing device that sequentially reads and executes instructions,
When an operand access request such as operand read or operand write is issued during instruction execution, this element triggers one machine if the bank is different.
A memory access method characterized in that a preceding instruction read request is issued after a cycle delay, and in the case of the same bank, the preceding instruction read request is invalidated.