JPH01124049A - Microprocessor - Google Patents

Abstract

PURPOSE:To dispense with the access of an external memory and to rapidly recede information by receding information indicating the internal information o a microprocessor to a rapid buffer memory in the microprocessor only when a preliminarily fixed mode is specified. CONSTITUTION:When the microprocessor 1 is driven by a system debugging mode through a debugging mode specification signal line 11, a built-in cache memory 7 does not act as an ordinary cache memory. At the time of inputting an interruption from the external or generating an exception, a control unit 3 in the microprocessor 1 stores information relating to the internal state of the microprocessor 1 in the entry of a preliminarily determined data cache 14 in the memory 7 to start exception processing. Consequently, the built-in cache memory 7 can be used for receding the internal state of the microprocessor 1 in the debugging mode in addition to the original function of the memory 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and particularly to a microprocessor' having a built-in cache memory.

[Prior Art] FIG. 5 is a block diagram of a conventional microprocessor having a built-in cache memory, MC6802032b.
It Microprocessor User'
s Manual", pages 1 and 2. In FIG. 5, the microprocessor 21 includes a sequencer 22, a control unit 23, an execution unit 24, an instruction fetch and decode unit 25, and a bus control unit 26. and a built-in cache memory 27, and exchanges information with the outside of the microprocessor via an address bus 28, a data bus 29, and a control bus 30.

Figure 6 is from “VLSI DESIGN” magazine, 1984.
, November, page 26, and FIG. 4 is a flow diagram thereof.

Next, the operation of the conventional microprocessor will be explained with reference to FIGS. 4 to 6. The built-in cache memory 27 in FIG. 5 is a set associative memory that stores instruction codes and their extensions, distinguishes between programs and data, and does not cache data. As shown in FIG. 6, the built-in cache memory 27 consists of two fields: an address tag 32 and a data cache 34. Address tag 32 holds the upper bits of the address for each entry, and data cache 34 holds fixed word length data from the storage location indicated by address tag 32. The lower bits of the program counter 33 decoded by the address decoder 37 indicate one entry of the address tag 32 and the corresponding entry of the data cache 34. If the contents of the entry in the designated address tag 32 match the upper bits of the program counter 33, that is, if there is a hit, the instruction code is transferred from the built-in cache memory 27 to the instruction fetch decode unit 25, and executed by the execution unit 24. executed. If they do not match, the bus control unit 26 executes an instruction fetch from outside the microprocessor 21, and the instruction fetch decode unit 26 executes an instruction fetch from outside the microprocessor 21.
5 and the data cache 34 of the built-in cache memory 27
The instruction code is stored in . In other words, as shown in FIG.
By setting it to 3, any entry in the built-in cache memory 27 can be accessed, and if the cache access is not successful, the address can be input to the address tag in response to an external instruction fetch. At the same time, the instruction code can be set in the data cache 34 of the built-in cache memory 27. On the other hand, if the cache access is successful, the contents of the data cache 34 are output to the data bus 29, so that they can be read.

Data is read by an external data bus (not shown) and address bus for accessing the outside of the microprocessor chip.

[Problems to be Solved by the Invention] Conventional microprocessors are configured as described above, and the cache memory is used only in its original usage, and no microprocessor has any further functionality.

Therefore, this invention was made to solve the above-mentioned problems, and in addition to the original cache memory function in a microprocessor equipped with a cache memory, it is possible to save the internal state of the microprocessor during debug mode. The object of the present invention is to obtain a microprocessor equipped with a cache memory that can also be used to store data.

[Means for Solving the Problems] In the microprocessor according to the present invention, when a predetermined mode is specified by the mode specifying means, when saving information regarding the internal state of the microprocessor, the control means saves the information regarding the internal state of the microprocessor. It controls the storage of information in a built-in high-speed buffer memory, and also allows reference to information regarding the internal state of the microprocessor stored in the high-speed buffer memory.

[Operation] When a predetermined mode is specified, the high-speed buffer memory of the present invention can save and store information regarding the internal state of the microprocessor, and can refer to it as necessary.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a microprocessor according to an embodiment of the present invention. In FIG. 1, a microprocessor 1 includes a sequencer 2. Control unit 3. Execution unit 4. Instruction fetch decode unit 5. It is composed of a bus control unit 6 and a built-in cache memory 7, and exchanges information with the outside of the microprocessor through an address bus 8, a data bus 9, and a control bus 10, and switches the operating mode of the microprocessor 1 through a debug mode designation signal line 11. . In this embodiment, the built-in cache memory 7 can be accessed from outside the microprocessor via the address bus 8 and data bus 9 in the debug mode.

FIG. 2 is a block diagram showing the operation of the built-in cache memory 7 of the microprocessor 1 shown in FIG.
The figure is a flow diagram.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. 1 to 3. In the normal operation mode, the built-in cache memory 7 is a set associative memory that stores instruction codes and their extensions as in the conventional example, and distinguishes between programs and data, and does not cache data.

In the normal mode, the same operation as in the conventional example shown in FIG. 4 is performed, so the explanation will be omitted.

Microprocessor 1 uses debug mode designation signal line 11
Therefore, when operating in the system debug mode, the built-in cache memory 7 does not operate as an original cache memory.

When an interrupt is input from the outside or an exception occurs, the control unit 3 of the microprocessor 1 stores information regarding the internal state of the microprocessor 1 in a predetermined entry in the data cache 14 of the built-in cache memory 7. and start exception handling. Here, the information regarding the internal state of the microprocessor 1 includes status information, a count value of a program counter, a value of a register, and the like.

The control unit 3 transfers information regarding the internal state stored in the built-in cache memory 7 to a general-purpose register (not shown) using a special instruction in an exception handling routine, or stops the microprocessor 1 based on a command from outside the microprocessor 1. This allows the built-in cache memory 7 to be accessed from the outside. In other words, when any entry in the cache memory 7 is specified by the address bus 8 from the outside, the data cache 14
The specified contents are read out via the data bus 9 and referred to.

In addition, in the two series of embodiments, an example in which the built-in cache memory is a set-associative instruction cat memory is shown that performs debug mode operation, but the built-in cache memory can be used either in a fully associative method or in a direct mapping method. There may be. Further, the same effect as described above is achieved not only in a cache memory that caches instruction codes but also in a cache memory that also caches data.

[Effects of the Invention] As described above, according to the present invention, when a predetermined mode is specified, information indicating internal information of the microprocessor is saved to a high-speed buffer memory provided within the microprocessor. Therefore, there is no need to access external memory, and information can be saved at high speed. Also, the information can be referenced by the microprocessor or an external device when needed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprocessor according to an embodiment of the present invention. FIG. 2 is a block diagram showing the operation of the built-in cache memory of the microprocessor shown in FIG. 1. FIG. 3 is a flow diagram for explaining the operation of one embodiment of the present invention. FIG. 4 is a flow diagram illustrating the operation of a conventional microprocessor and an embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of a conventional microprocessor. FIG. 6 is a block diagram showing the operation of a cache memory built into the conventional microprocessor shown in FIG. In the figure, 1 is a microprocessor, 2 is a sequencer, 3 is a control unit, 4 is an execution unit, 5 is an instruction fetch decode unit, 6 is a bus control unit, 7 is a built-in cache memory, 8 is an address bus, and 9 is a data bus. , 10 is a control bus, 11 is a debug mode designation signal line, 12 is an address tag, 13 is a program counter, 1
4 is a data cache, and 17 is an address decoder.

Claims (5)

[Claims] (1) In a microprocessor with a built-in high-speed buffer memory, mode specifying means for specifying a predetermined mode; and when the predetermined mode is specified by the mode specifying means, information regarding the internal state of the microprocessor is saved. control means for controlling the information to be stored in the high-speed buffer memory, and for controlling the information stored in the high-speed buffer memory regarding the internal state of the microprocessor to be referenced. , microprocessor. (2) The microprocessor according to claim 1, wherein the high-speed buffer memory is a cache memory. (3) the predetermined mode is a debug mode;
A microprocessor according to claim 1 or 2. (4) When the predetermined mode is specified by the mode specifying means, the high-speed buffer memory
2. The microprocessor according to claim 1, wherein the microprocessor can be accessed in response to being given a predetermined instruction. (5) The high-speed buffer memory includes a plurality of entries, and when the predetermined mode is specified by the mode specifying means, the high-speed buffer memory stores the corresponding 2. A microprocessor as claimed in claim 1, wherein a designated entry is accessible.