JPH0690732B2 - Microprocessor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor including a cache memory.

[Prior Art] FIG. 5 is a block diagram of a conventional microprocessor having a built-in cache memory.
It is published on pages 1 and 2 of "Oprocessor User's Manual." In FIG. 5, the microprocessor 21 includes a sequencer 22, a control unit 23, and an execution unit.
24, instruction fetch decode unit 25, bus control unit
26 and a built-in cache memory 27, information is exchanged with the outside of the microprocessor through an address bus 28, a data bus 29 and a control bus 30.

FIG. 6 is a block diagram showing the operation of the built-in cache memory published in "VLSI DESIGN" magazine, 1984, November, page 26, and FIG. 4 is a flow chart thereof.

Next, the operation of the conventional microprocessor will be described with reference to FIGS. The built-in cache memory 27 in FIG. 5 is a set associative memory that stores an instruction code and its extension, distinguishes between a program and data, and does not cache data. As shown in FIG. 6, the internal cache memory 27 has an address tag 32.
And the data cache 34. The address tag 32 holds the upper bits of the address for each entry, and the data cache 34 holds the fixed word length data from the storage location indicated by the address tag 32. The lower bits of the program counter 33 decoded by the address decoder 37 indicate one entry of the address tag 32 and the corresponding entry of the data cache 34. When the content of the entry of the designated address tag 32 matches the upper bits of the program counter 33, that is, when a hit occurs, the instruction code is transferred from the internal cache memory 27 to the instruction fetch decode unit 25,
It is executed by the execution unit 24. If they do not match, the bus control unit 26 executes the instruction fetch from the outside of the microprocessor 21, and the instruction code is stored in the instruction fetch decode unit 25 and the data cache 34 of the internal cache memory 27. That is, the fourth
As shown in the figure, by setting the address to be accessed next to the program counter 33, it is possible to access any entry of the internal cache memory 27, and if no cache access hits, An address can be input to an address tag in response to an instruction fetch, and an instruction code can be set in the data cache 34 of the internal cache memory 27. On the other hand, when the cache access is hit, the contents of the data cache 34 are output to the data bus 29, and thus the data can be read. Data is read by an external data bus (not shown) and an address bus for accessing the outside of the microprocessor chip.

[Problems to be Solved by the Invention] The conventional microprocessor is configured as described above, and the cache memory is used only in its original usage, and none has been provided with a further function.

Therefore, the present invention has been made to solve the above problems, and in a microprocessor equipped with a cache memory, in addition to the original function of the cache memory, the internal state of the microprocessor is saved in the debug mode. The purpose is to obtain a microprocessor with a cache memory that can also be used to

[Means for Solving Problems] In the microprocessor according to the present invention, when the mode specifying means specifies a predetermined mode, when the information about the internal state of the microprocessor is saved, the control means The information is controlled to be stored in the built-in high-speed buffer memory, and the information about the internal state of the microprocessor stored in the high-speed buffer memory can be referred to.

[Operation] In the high-speed buffer memory according to the present invention, when a predetermined mode is designated, information on the internal state of the microprocessor can be saved and stored, and can be referred to when necessary.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a microprocessor according to an embodiment of the present invention. In FIG. 1, a microprocessor 1 comprises a sequencer 2, a control unit 3, an execution unit 4, an instruction fetch decode unit 5, a bus control unit 6 and a built-in cache memory 7, and an address bus 8, a data bus 9 and a control bus. Information is exchanged with the outside of the microprocessor by 10 and the operation mode of the microprocessor 1 is switched by the debug mode designation signal line 11. In this embodiment, in debug mode,
The built-in cache memory 7 can be accessed from outside the microprocessor by the address bus 8 and the data bus 9.

FIG. 2 is a block diagram showing the operation of the internal cache memory 7 of the microprocessor 1 shown in FIG.
The figure is the flow chart.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. In the normal operation mode, the built-in cache memory 7 is a set associative memory that stores an instruction code and its extension as in the conventional example, distinguishes between a program and data, and does not cache data. In the normal mode, the same operation as the conventional example shown in FIG.

When the microprocessor 1 is operating in the system debug mode by the debug mode designation signal line 11,
The built-in cache memory 7 does not operate as an original cache memory. When an interrupt is input from the outside or an exception occurs, the control unit 3 of the microprocessor 1 stores information about the internal state of the microprocessor 1 in a predetermined data cache 14 entry of the internal cache memory 7. And start exception handling. Here, the information regarding the internal state of the microprocessor 1 is status information, the count value of the program counter, the value of the register, and the like.

The control unit 3 transfers the information about the internal state stored in the built-in cache memory 7 to a general-purpose register (not shown) by a special instruction in the exception handling routine, or stops the microprocessor 1 by a command from the outside of the microprocessor 1. Then, the built-in cache memory 7 can be accessed from the outside. That is, when any entry of the cache memory 7 is designated by the address bus 8 from the outside, the designated content of the data cache 14 is read out through the data bus 9 and referred to.

In the above-described embodiment, the one in which the built-in cache memory is the set associative instruction cache memory performs the debug mode operation, but the built-in cache memory may be the full associative system or the direct mapping system. . Further, not only the instruction code is cached but also a cache memory that caches data also has the same effect as described above.

As described above, according to the present invention, when the predetermined mode is designated, the information indicating the internal information of the microprocessor is saved in the high-speed buffer memory provided in the microprocessor. Therefore, it is not necessary to access the external memory, and the information can be saved at high speed. Further, the information can be referred to by a microprocessor or an external device when the information is needed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a microprocessor according to an embodiment of the present invention. FIG. 2 is a block diagram showing the operation of the internal cache memory of the microprocessor shown in FIG. FIG. 3 is a flow chart for explaining the operation of the embodiment of the present invention. FIG. 4 is a flow chart for explaining the operation of the conventional microprocessor and one embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of a conventional microprocessor. FIG. 6 is the fifth
It is a block diagram showing operation | movement of the cache memory incorporated in the conventional microprocessor shown in the figure. In the figure, 1 is a microprocessor, 2 is a sequencer, 3 is a control unit, 4 is an execution unit, 5 is an instruction fetch decode unit, 6 is a bus control unit, 7 is a built-in cache memory, 8 is an address bus, and 9 is a data bus. , 10 is a control bus, 11 is a debug mode designation signal line,
12 is an address tag, 13 is a program counter, 14 is a data cache, and 17 is an address decoder.

Claims (5)

[Claims] 1. A microprocessor with a built-in high-speed buffer memory, wherein a mode designating means for designating a predetermined mode and information about an internal state of the microprocessor when the predetermined mode is designated by the mode designating means. In order to save the information, control means for controlling the information to be stored in the high-speed buffer memory, and controlling so as to refer to the information on the internal state of the microprocessor stored in the high-speed buffer memory. Equipped with a microprocessor. 2. The microprocessor according to claim 1, wherein the high speed buffer memory is a cache memory. 3. The microprocessor according to claim 1 or 2, wherein the predetermined mode is a debug mode. 4. The high-speed buffer memory can be accessed when a predetermined command is given when the predetermined mode is specified by the mode specifying means. The microprocessor according to item 1. 5. The high speed buffer memory includes a plurality of entries, and when any one of the plurality of entries is designated from the outside when the predetermined mode is designated by the mode designating means. The microprocessor according to claim 1, wherein the specified entry is accessible.