JPH0776943B2 - Method for testing system memory of data processing system having cache memory and data processing system having cache memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system having a cache memory, and more particularly to testing a system memory.

[0002]

2. Description of the Related Art In a data processing system such as a personal computer, a system memory (main memory) is usually tested when the power is turned on. The program for this system memory test is usually included in a POST (Power On Self Test) program, and this test reads data after writing a predetermined pattern of data in the system memory.
This is done by making sure that the correct reading and writing has been performed. Therefore, if you actually need to read or write data to the system memory and your data processing system has cache memory, you should disable the cache memory before you test it. It was Therefore, for normal program execution, a cache
Even in the data processing system with the memory, it was not possible to expect a high execution speed for executing the test program in the system memory.

Further, even in a personal computer which employs a high-performance CPU, when the cache memory is disabled, that is, the system
When a memory test is performed, the execution speed of the memory test may be reduced even though a high performance CPU is adopted. An example of such a case is that the fetch queue (the circuit that holds the prefetched program inside the CPU) has 16 bytes and the fetch queue is 3
Observed when changing to a 2-byte CPU. In a CPU with a fetch queue of 32 bytes, if the fetch queue and the internal cache memory are connected by 128 bits (16 bytes), the fetch queue can be filled at high speed. However, if the data bus bit widths are both 32 bits (4 bytes), in order to fill the fetch queue, a 16-byte fetch
A CPU with a queue only requires four memory reads, whereas a C with a 32-byte fetch queue
PU requires 8 memory reads. CPU JM
Every P instruction the contents of the fetch queue are cleared and the fetch queue must be refilled. Therefore, when the cache memory is disabled and the memory test is performed, the execution speed becomes slower in the case of the high-performance CPU.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to enable rapid testing of system memory in a data processing system with cache memory.

[0005]

In order to achieve the above object, in the method of testing a system memory according to the present invention, a code portion in a test program is fetched into a cache memory when the test program is executed. The data part is not stored in the cache memory.

Further, the data processing system according to the present invention includes a CPU, a system memory for storing a program executed by the CPU, and the CPU accessing the code portion or the data portion of the program. A status signal generating means for generating at least a code / data signal indicating whether or not to operate, a cache memory, and a cache control signal generating means for generating a signal for enabling or disabling the cache memory. However, the cache control signal generating means is made responsive to the output signal of the state signal generating means.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the data processing system according to the present invention. In the figure, the data processing system includes a microprocessor (CPU) 10, a DMA controller 12, a memory controller 14, a system controller 16, a timing signal line 22, and a POST (power
ROM 24, memory bus 26, system bus 28, system memory 3 for storing an on-self test program and a BIOS (basic input / output system)
It has 0 and an expansion card 32.

FIG. 1 shows the essential parts of the above embodiment in more detail. In the figure, the microprocessor 10 has a cache memory 40 and a status signal generating means 42 built therein. The cache memory 40 is enabled (the cache control signal is at the low level) or disabled (the cache control signal is at the high level) according to the cache control signal (low active) input to the CPU 10.
It is supposed to be done. The state signal generating means 42 is C
The PU 10 generates a data / code signal (+ D / -C signal) indicating whether to access the code portion or the data portion of the program stored in the system memory 30. + D / -C When the signal is high level, it indicates that the CPU accesses the data portion, +
When the D / -C signal is low, it indicates that the CPU is accessing the code portion. In addition to this, the state signal generating means 42 generates a memory / IO signal (+ M / -IO signal) indicating whether the address signal output by the CPU 10 is a memory address signal or an IO address signal. When the + M / -IO signal is high level,
The address signal output by the CPU 10 indicates that it is a memory address, and when the + M / -IO signal is at a low level, it indicates that the address signal output by the CPU 10 is an IO address.

The memory controller 14 has an address decoder 50 and cache control signal generating means 60. The address decoder 50 decodes the address signal from the CPU 10 and outputs a + cache / -non-cache signal according to the value of the address output by the CPU 10. That is, the address decoder 50 is a circuit for designating whether to cache according to the value of the address. When the + Cash /-non-cache signal is at a high level, it indicates that the address operates the cache function, and the + Cash / -non-cache signal is at a low level.
When the level is set, it indicates that the address cannot operate the cache function. The address at which the cache function works and the address at which the cache function does not work depend on the configuration of the data processing system. For example, the address of the memory on the expansion card 32 may not work the cache function. It is normal.

The cache control signal generating means 60 includes a register 52, an AND circuit 54, a 3-input NOR circuit 56, and an NA.
It has an ND circuit 58, a NOT circuit 62, a NOR circuit 64, and an OR circuit 66. The register 52 is the CPU 1
It is a so-called I / O register arranged at a predetermined address in the IO space accessible by 0. However, CPU
It may be arranged in the memory space depending on the configuration of 10. Further, the register 52 has a data width of, for example, 8 bits, and the cache memory 40 has a data value of those bits.
Specifies various functions associated with. Of the 8 bits of register 52, bit 2 and bit 0 are cache control bits. Bit 2 as shown in FIG.
When the value of is 0, only the code part is cached, and when the value of bit 2 is 1, both the code part and the data part are cached. When the value of bit 0 is 0, the cache function is enabled , and when the value of bit 0 is 1, the cache function is disabled. However, the above-described designation by the value of bit 2 is valid only when the value of bit 0 is 0, that is, the cache function is designated to be enabled.

In FIG. 1, the output signal of the address decoder 50 is input to the AND circuit 54. AND circuit 5
The other input of 4 is the + M / -IO signal from the CPU 10. Therefore, the high level output of the AND circuit 54 indicates that the address from the CPU 10 is a memory address and a memory address within the range to be cached.

The + D / -C signal from the CPU 10 is input to the 3-input NOR circuit 56 of the cache control signal generating means 60. The remaining two inputs of the 3-input NOR circuit 56 are both outputs of the register 52, one of which is a + cache disable / −enable signal, and the other of which is a + code only cache disable / −enable signal. Is. The + cache disable / −enable signal, which can be understood by referring to the table of FIG. 3, is low level when the value of bit 0 of the register 52 is 0, and when the value of bit 0 is 1. Is at a high level. Also, the + code only cache disable / -enable signal is bit 2 of register 52.
Is low when the value of is 0 and high when the value of bit 2 is 1. However, as also noted in FIG. 3, the function specification by the value of bit 2 is valid only when the value of bit 0 is 0, that is, when cache enable is specified. The system memory test program in the POST program instructs to write 0 as the value of bit 2.

The output signal of the 3-input NOR circuit 56 is high.
It becomes a level when all the signals of three inputs are low level. That is, POST sets the value of bit 2 to 0 when the value of bit 0 of register 52 is 0, and
It is when 10 accesses the code portion of the program. The output of the 3-input NOR circuit 56 is connected to one input of the NAND circuit 58 via the OR circuit 66. N
The output of the AND circuit 54 is connected to the other input of the AND circuit 58. When both the outputs of the AND circuit 54 and the NOR circuit 56 are high level, the output of the NAND circuit 58 becomes low level. The output of the NAND circuit 58 is a cache control signal sent to the CPU 10, and the cache memory 40 operates only when this cache control signal is at a low level.

The other input of the OR circuit 66 is NO.
The output of the R circuit 64 is connected, one input of the NOR circuit 64 is a + cache disable / −enable signal, and the other input is a + code only cache disable / −enable signal by the NOT circuit 62. The inverted signal. Therefore, the output of the NOR circuit 64 becomes high level when the + cache disable / -enable signal is low level (designation of cache enable), and the + code only cache disable /- This is when the enable signal is at the high level. Therefore, also in this case, the cache memory 40 operates. However, in this case, only the code part is not cached.

According to this embodiment, the system
The memory 30 can be tested quickly. The time required to test the system memory 30 increases as the storage capacity of the system memory 30 increases. Therefore, as shown in FIG. 4, as the storage capacity of the system memory 30 increases, the effect of shortening the test time according to the present embodiment becomes more remarkable. In addition, the address under test (test address) may be displayed on the screen to show the progress of the test. In this case, according to the present embodiment, the test address progresses at a high speed, and therefore the test address is first displayed to the operator after the system power is turned on. Can give a good impression.

In the above embodiment, the cache memory is built in the CPU, but the present invention is not limited to the case where the cache memory is built in the CPU, and the cache memory is built in the CPU. May be provided outside. Further, although the cache memory is the general-purpose cache memory in the above-described embodiment, the present invention is not limited to the general-purpose cache memory, and the cache memory includes the code cache memory and the data cache memory. And both or either of them may be used.

[0017]

As described above, according to the present invention, it is possible to quickly test the system memory of the data processing system having the cache memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a data processing system according to the present invention.

FIG. 2 is a block diagram showing an overall configuration of the embodiment.

FIG. 3 is a table showing a relationship between cache control bits held in a register and cache control contents in the embodiment.

FIG. 4 is a graph showing the time required for the system memory according to the above embodiment in comparison with the case of the conventional example.

[Explanation of symbols]

 10 Mylox Processor (CPU) 12 DMA Controller 14 Memory Controller 16 System Controller 18 System Clock Oscillator 22 Timing Signal Line 24 ROM 26 Memory Bus 28 System Bus 30 System Memory 32 Expansion Card 40 Cache Memory 42 Status Signal generating means 50 Address decoder 52 Register 60 Cache control signal generating means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Yamazaki 1623 Shimotsuruma, Yamato-shi, Kanagawa 14 Yamabe Works, IBM Japan, Ltd. (56) Reference JP-A-2-17552 (JP, A) ) JP 63-201850 (JP, A)

Claims (7)

[Claims] 1. A method of testing the system memory of a data processing system comprising a cache memory having a CPU, a system memory and a cache memory, the method comprising: A method for testing a system memory of a data processing system having a cache memory, wherein a code portion in a program is loaded into the cache memory but a data portion is not loaded into the cache memory. 2. The cache memory is a general-purpose cache capable of caching both a data portion and a code portion.
A method for testing a system memory of a data processing system having a cache memory according to claim 1, which is a memory. 3. A CPU, a system memory for storing a program executed by the CPU, the sheet
Run a program for stem memory testing
Sometimes the CPU accesses the code part of the program.
Code indicating whether to access the data part or
A data processing system comprising: a status signal generating means for generating a data signal ; a cache memory; and a cache control signal generating means for generating a signal for enabling or disabling the cache memory, A data processing system comprising a cache memory, wherein the cache control signal generating means is responsive to an output signal of the status signal generating means. 4. The cache memory is a general-purpose cache capable of caching both a data part and a code part.
A data processing system comprising the cache memory of claim 3, which is a memory. 5. A data processing system having a cache memory according to claim 4, wherein said cache memory is incorporated in said CPU. 6. A data processing system having a cache memory according to claim 3, wherein said status signal generating means is incorporated in said CPU. Wherein said cache control signal generating means includes a register accessible by the CPU, and generates a signal that enables or disables the generic cache memory according to the value of the register, wherein
A data processing system comprising a cache memory according to item 6 .