TW234173B - Method for testing system memory - Google Patents

Method for testing system memory

Info

Publication number
TW234173B
TW234173B TW080108171A TW80108171A TW234173B TW 234173 B TW234173 B TW 234173B TW 080108171 A TW080108171 A TW 080108171A TW 80108171 A TW80108171 A TW 80108171A TW 234173 B TW234173 B TW 234173B
Authority
TW
Taiwan
Prior art keywords
cache memory
data
cpu
code
fetched
Prior art date
Application number
TW080108171A
Other languages
Chinese (zh)
Inventor
Satoshi Yamazaki
Toshiaki Fukushima
Mitsuhiro Goda
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW234173B publication Critical patent/TW234173B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A method used for data processing system with cache memory, in which the data processing system includes: 1. CPU; 2. system memory storing the CPU executable codes; 3. status signal generating device, at least being able to generate code/data signal to instruct the CPU to access the code or data; 4. cache memory; 5. cache control signal generating device for generating enable or disable signal for cache memory. The method includes the steps that when executing testing program, the code part of the testing program is fetched into the cache memory, and none of the data part is fetched into the cache memory.
TW080108171A 1991-10-11 1991-10-16 Method for testing system memory TW234173B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3290407A JPH0776943B2 (en) 1991-10-11 1991-10-11 Method for testing system memory of data processing system having cache memory and data processing system having cache memory

Publications (1)

Publication Number Publication Date
TW234173B true TW234173B (en) 1994-11-11

Family

ID=17755619

Family Applications (1)

Application Number Title Priority Date Filing Date
TW080108171A TW234173B (en) 1991-10-11 1991-10-16 Method for testing system memory

Country Status (3)

Country Link
JP (1) JPH0776943B2 (en)
KR (1) KR930008620A (en)
TW (1) TW234173B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200911157A (en) * 2007-09-13 2009-03-16 Nifco Taiwan Corp Side-open buckle

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63201850A (en) * 1987-02-18 1988-08-19 Matsushita Electric Ind Co Ltd On chip cash memory
JPH0217552A (en) * 1988-07-06 1990-01-22 Nec Corp Performance data measuring system

Also Published As

Publication number Publication date
JPH0776943B2 (en) 1995-08-16
KR930008620A (en) 1993-05-21
JPH05127994A (en) 1993-05-25

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