JPS6429942A - System for verificating machine check processing - Google Patents

System for verificating machine check processing

Info

Publication number
JPS6429942A
JPS6429942A JP62184675A JP18467587A JPS6429942A JP S6429942 A JPS6429942 A JP S6429942A JP 62184675 A JP62184675 A JP 62184675A JP 18467587 A JP18467587 A JP 18467587A JP S6429942 A JPS6429942 A JP S6429942A
Authority
JP
Japan
Prior art keywords
program
interruption
machine check
cpu
check processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62184675A
Other languages
Japanese (ja)
Inventor
Itsumi Sugiyama
Hiroshi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62184675A priority Critical patent/JPS6429942A/en
Publication of JPS6429942A publication Critical patent/JPS6429942A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To realize a machine check processing at all timings, by providing an interruption processing means which changes a part of the program of a program memory executed by a CPU in order at every addition of an interruption signal from a timer interruption means. CONSTITUTION:The CPU 1 is a processor which performs the machine check processing, and executes the program stored in the program memory 2. The timer interruption means 3 adds the interruption signal on the CPU 1 at a specific time interval, and for example, the CPU 1 executes the interruption processing means 4 at every addition of the interruption signal, and changes an instruction in the program memory 2 in order. The rewrite of the program is recognized equivalently as the fault of hardware, and the fault at all timings under the execution of the program can be generated by rewriting the program in order. In such a way, it is possible to check the machine check processing at all timings.
JP62184675A 1987-07-25 1987-07-25 System for verificating machine check processing Pending JPS6429942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184675A JPS6429942A (en) 1987-07-25 1987-07-25 System for verificating machine check processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184675A JPS6429942A (en) 1987-07-25 1987-07-25 System for verificating machine check processing

Publications (1)

Publication Number Publication Date
JPS6429942A true JPS6429942A (en) 1989-01-31

Family

ID=16157393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184675A Pending JPS6429942A (en) 1987-07-25 1987-07-25 System for verificating machine check processing

Country Status (1)

Country Link
JP (1) JPS6429942A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067300A (en) * 1989-10-24 1991-11-26 Yoshida Kogyo K.K. Method of attaching curtain wall units to a building skeleton framework

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5067300A (en) * 1989-10-24 1991-11-26 Yoshida Kogyo K.K. Method of attaching curtain wall units to a building skeleton framework

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