JPS6476225A - Coprocessor system - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines between a main processor and a sub-processor and to attain sequence control from the main processor to the sub-processor by providing a selector, an OR circuit and a control memory address register, etc. CONSTITUTION:A machine language instruction, which is stored to an instruction register 3, is decoded by an instruction decoder 4 and the top address of a micro-instruction processing routine is generated and set to a control memory address register 5. Simultaneously, the low order 8 bits of the top address are sent through a selector 16 and a control memory address signal line 11 to a sub-processor 2. When the decoded machine language instruction is an instruction so as to use the processor 2, a signal to show the line 11 is effective is sent through an OR circuit 7 and a control memory address effective and ineffective signal line 10 to the processor 2. Then, the processor 2 fetches a value received by the line 11 into a control memory address register 12. Thus, the control memory address of the processor 2 is generated to correspond to the machine language instruction and the sequence control can be executed by the small number of signal lines.