JPS6421628A - Arithmetic processing unit - Google Patents

Arithmetic processing unit

Info

Publication number
JPS6421628A
JPS6421628A JP17936387A JP17936387A JPS6421628A JP S6421628 A JPS6421628 A JP S6421628A JP 17936387 A JP17936387 A JP 17936387A JP 17936387 A JP17936387 A JP 17936387A JP S6421628 A JPS6421628 A JP S6421628A
Authority
JP
Japan
Prior art keywords
instruction
given
destination address
branched
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17936387A
Other languages
Japanese (ja)
Inventor
Hideki Ando
Takeo Nakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17936387A priority Critical patent/JPS6421628A/en
Priority to DE19873740877 priority patent/DE3740877A1/en
Publication of JPS6421628A publication Critical patent/JPS6421628A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To attain high speed processing by adopting the constitution in such a way that an instruction of a branched destination address is stored in a cache memory and accessed. CONSTITUTION:When an instruction decoded by a decoder 21 in a decode circuit 3 is a branch instruction, a branched destination address is given to an associate memory CAM 62 of a cache memory 6. When the access is hit, a corresponding instruction is outputted from a RAM 61 and given to a multiplexer MUX 4. On the other hand, the instruction is processed by the circuit 3 and in case of the established branch, a high level signal is given to an AND gate 5 and a high level signal is given to an MUX 4 and the instruction from the RAM 61 is given to an instruction register 11. Thus, the instruction at the branched address is processed in the decoders 22, 23 afterward in succession to the instruction and no waste time is caused. On the other hand, if the access of the memory 6 by the branched destination address is mis-hit, no instruction is given from the RAM 61 but when the branch condition is established, the memory 6 is revised by the branched destination address.
JP17936387A 1987-07-17 1987-07-17 Arithmetic processing unit Pending JPS6421628A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP17936387A JPS6421628A (en) 1987-07-17 1987-07-17 Arithmetic processing unit
DE19873740877 DE3740877A1 (en) 1987-07-17 1987-12-02 System and method to increase the data throughput performance in a pipeline microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17936387A JPS6421628A (en) 1987-07-17 1987-07-17 Arithmetic processing unit

Publications (1)

Publication Number Publication Date
JPS6421628A true JPS6421628A (en) 1989-01-25

Family

ID=16064543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17936387A Pending JPS6421628A (en) 1987-07-17 1987-07-17 Arithmetic processing unit

Country Status (2)

Country Link
JP (1) JPS6421628A (en)
DE (1) DE3740877A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03191427A (en) * 1989-12-20 1991-08-21 Nec Corp Microprocessor
JPH0527971A (en) * 1991-07-24 1993-02-05 Nec Corp Information processor
JPH05128001A (en) * 1991-11-07 1993-05-25 Koufu Nippon Denki Kk Information processor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051948A (en) * 1983-08-31 1985-03-23 Hitachi Ltd Branch destination buffer storage device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03191427A (en) * 1989-12-20 1991-08-21 Nec Corp Microprocessor
JPH0527971A (en) * 1991-07-24 1993-02-05 Nec Corp Information processor
JPH05128001A (en) * 1991-11-07 1993-05-25 Koufu Nippon Denki Kk Information processor

Also Published As

Publication number Publication date
DE3740877A1 (en) 1989-02-02

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