JPS6481056A - Data processor - Google Patents

Data processor

Info

Publication number
JPS6481056A
JPS6481056A JP62237146A JP23714687A JPS6481056A JP S6481056 A JPS6481056 A JP S6481056A JP 62237146 A JP62237146 A JP 62237146A JP 23714687 A JP23714687 A JP 23714687A JP S6481056 A JPS6481056 A JP S6481056A
Authority
JP
Japan
Prior art keywords
instruction
data processing
memory
address
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62237146A
Other languages
Japanese (ja)
Other versions
JP2533893B2 (en
Inventor
Akira Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62237146A priority Critical patent/JP2533893B2/en
Publication of JPS6481056A publication Critical patent/JPS6481056A/en
Application granted granted Critical
Publication of JP2533893B2 publication Critical patent/JP2533893B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To improve the arithmetic executing speed by adding a cache memory into a data processor to store an instruction for decision of the data processing procedure. CONSTITUTION:When a digital signal processor DSP processes data based on a program written into an external instruction memory EM, a relevant address is designated by an address signal A1 produced by a control circuit CONT. The instruction word read out by said address designation is supplied to a DSP and then supplied to an instruction decoder DEC via multiplexers MPX1 and 2 to be executed there. At the same time, the instruction word is written into an instruction cache memory CM. Thus the second and subsequent data processing jobs are carried out by the instruction words stored in the memory CM. Then the data processing speed is increased.
JP62237146A 1987-09-24 1987-09-24 Data processing device Expired - Fee Related JP2533893B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237146A JP2533893B2 (en) 1987-09-24 1987-09-24 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237146A JP2533893B2 (en) 1987-09-24 1987-09-24 Data processing device

Publications (2)

Publication Number Publication Date
JPS6481056A true JPS6481056A (en) 1989-03-27
JP2533893B2 JP2533893B2 (en) 1996-09-11

Family

ID=17011088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237146A Expired - Fee Related JP2533893B2 (en) 1987-09-24 1987-09-24 Data processing device

Country Status (1)

Country Link
JP (1) JP2533893B2 (en)

Also Published As

Publication number Publication date
JP2533893B2 (en) 1996-09-11

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees