JPS6418841A - Information processor for prefetching instruction - Google Patents

Information processor for prefetching instruction

Info

Publication number
JPS6418841A
JPS6418841A JP17636087A JP17636087A JPS6418841A JP S6418841 A JPS6418841 A JP S6418841A JP 17636087 A JP17636087 A JP 17636087A JP 17636087 A JP17636087 A JP 17636087A JP S6418841 A JPS6418841 A JP S6418841A
Authority
JP
Japan
Prior art keywords
instruction
register
address
branch
branching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17636087A
Other languages
Japanese (ja)
Other versions
JPH0715662B2 (en
Inventor
Masahiko Yamamouri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17636087A priority Critical patent/JPH0715662B2/en
Publication of JPS6418841A publication Critical patent/JPS6418841A/en
Publication of JPH0715662B2 publication Critical patent/JPH0715662B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To avoid a case where the undesired instructions are taken out by performing the control so that a designated branch instruction receiver address is not registered into a branch history table by the prescribe address qualification. CONSTITUTION:The instruction words, the instruction addresses and the branching destination addresses are set to an instruction register 1, an instruction address register 5 and a branching destination address register 6 respectively from an advance control unit 8 via signal lines 105, 106 and 107 before a branch instruction is carried out. Then a branch deciding circuit 2 connected to the register 1 decides the presence or absence of branching. When the presence of branching is decided, the contents of both registers 5 and 6 are registered into a branch history table 7. At the same time, an address qualification detecting circuit 3 decodes the instruction words of the register 1 and disables the output of a gate 4 when the address qualification is detected.
JP17636087A 1987-07-14 1987-07-14 Information processing device for prefetching instructions Expired - Fee Related JPH0715662B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17636087A JPH0715662B2 (en) 1987-07-14 1987-07-14 Information processing device for prefetching instructions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17636087A JPH0715662B2 (en) 1987-07-14 1987-07-14 Information processing device for prefetching instructions

Publications (2)

Publication Number Publication Date
JPS6418841A true JPS6418841A (en) 1989-01-23
JPH0715662B2 JPH0715662B2 (en) 1995-02-22

Family

ID=16012253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17636087A Expired - Fee Related JPH0715662B2 (en) 1987-07-14 1987-07-14 Information processing device for prefetching instructions

Country Status (1)

Country Link
JP (1) JPH0715662B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260033A (en) * 1989-02-03 1990-10-22 Digital Equip Corp <Dec> Branch forecast
JP2008532142A (en) * 2005-02-24 2008-08-14 クゥアルコム・インコーポレイテッド Suppressing the update of the branch history register by a loop closing branch

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260033A (en) * 1989-02-03 1990-10-22 Digital Equip Corp <Dec> Branch forecast
JP2008532142A (en) * 2005-02-24 2008-08-14 クゥアルコム・インコーポレイテッド Suppressing the update of the branch history register by a loop closing branch
JP2011100466A (en) * 2005-02-24 2011-05-19 Qualcomm Inc Suppressing update of branch history register by loop-ending branch

Also Published As

Publication number Publication date
JPH0715662B2 (en) 1995-02-22

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees