JPS57193842A - Request conflict detecting system - Google Patents

Request conflict detecting system

Info

Publication number
JPS57193842A
JPS57193842A JP7666981A JP7666981A JPS57193842A JP S57193842 A JPS57193842 A JP S57193842A JP 7666981 A JP7666981 A JP 7666981A JP 7666981 A JP7666981 A JP 7666981A JP S57193842 A JPS57193842 A JP S57193842A
Authority
JP
Japan
Prior art keywords
instruction
preprocessing
load
storage
load instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7666981A
Other languages
Japanese (ja)
Inventor
Toshihisa Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7666981A priority Critical patent/JPS57193842A/en
Publication of JPS57193842A publication Critical patent/JPS57193842A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To save the hardware and to simplify the control, by detecting as OSC and an ISC with a common circuit and controlling them as the same processing. CONSTITUTION:A load instruction is appeared at a D stage when a storage instruction is at an A stage. If an operand address i between the storage instruction and the load instruction not coincide, since no input condition is established for gates j and k, and F//F8 remains reset and a line n is at (0). Thus, the progress of the preprocessing of the load instruction is not blocked and the execution of the instruction is advanced. If the operand address of the storage and load instructions coincide, since the input condition of the gates j and l is established, the F//F8 for conflict detection is set, the line n is at (1), and a preprocessing pipe line control section 4 judges that the conflict is detected to block the advance of the preprocessing of the load instruction.
JP7666981A 1981-05-22 1981-05-22 Request conflict detecting system Pending JPS57193842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7666981A JPS57193842A (en) 1981-05-22 1981-05-22 Request conflict detecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7666981A JPS57193842A (en) 1981-05-22 1981-05-22 Request conflict detecting system

Publications (1)

Publication Number Publication Date
JPS57193842A true JPS57193842A (en) 1982-11-29

Family

ID=13611816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7666981A Pending JPS57193842A (en) 1981-05-22 1981-05-22 Request conflict detecting system

Country Status (1)

Country Link
JP (1) JPS57193842A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0305639A2 (en) * 1987-09-03 1989-03-08 Director-General Of The Agency Of Industrial Science And Technology Vector computer
EP0340453A2 (en) * 1988-04-01 1989-11-08 Nec Corporation Instruction handling sequence control system
EP1172725A2 (en) * 2000-07-12 2002-01-16 Nec Corporation Vector scatter instruction control circuit and vector architecture information processing equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5112225A (en) * 1974-07-12 1976-01-30 Signode Corp
JPS5547524A (en) * 1978-09-28 1980-04-04 Nec Corp Data transmission device
JPS55147744A (en) * 1979-05-07 1980-11-17 Hitachi Ltd Memory controlling unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5112225A (en) * 1974-07-12 1976-01-30 Signode Corp
JPS5547524A (en) * 1978-09-28 1980-04-04 Nec Corp Data transmission device
JPS55147744A (en) * 1979-05-07 1980-11-17 Hitachi Ltd Memory controlling unit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0305639A2 (en) * 1987-09-03 1989-03-08 Director-General Of The Agency Of Industrial Science And Technology Vector computer
US4967350A (en) * 1987-09-03 1990-10-30 Director General Of Agency Of Industrial Science And Technology Pipelined vector processor for executing recursive instructions
EP0340453A2 (en) * 1988-04-01 1989-11-08 Nec Corporation Instruction handling sequence control system
EP1172725A2 (en) * 2000-07-12 2002-01-16 Nec Corporation Vector scatter instruction control circuit and vector architecture information processing equipment
EP1172725A3 (en) * 2000-07-12 2003-07-16 Nec Corporation Vector scatter instruction control circuit and vector architecture information processing equipment
US6816960B2 (en) 2000-07-12 2004-11-09 Nec Corporation Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution

Similar Documents

Publication Publication Date Title
ES8702010A1 (en) System for by-pass control in pipeline operation of computer.
JPS57193842A (en) Request conflict detecting system
JPS6472237A (en) Address calculation system
JPS55164922A (en) Multimicrocomputer
JPS57164343A (en) Check point save system
JPS55154653A (en) Interruption distributing system to multiprocessor
JPS57174747A (en) Device diagnosing system
JPS57109057A (en) Automatic switching system of dual-processor system
JPS5697169A (en) Multidata processing system
JPS55157022A (en) Output circuit for microcomputer
JPS5730056A (en) Failure processing system for data processing system
JPS5552155A (en) Check system of arithmetic logical operation unit
JPS5640935A (en) Initial set processing system for multiprocessor system
JPS5566015A (en) Shared line state detection system
JPS57199056A (en) Execution and monitoring device for control program
JPS5591040A (en) Runaway monitor system for microprocessor
JPS55102062A (en) Fail safe system
JPS57161921A (en) Signal processing system
JPS57207952A (en) Instruction controlling system
JPS5279736A (en) Memory error detecting control system
JPS5499882A (en) Plant supervisory controller
JPS5451427A (en) Memory unit
JPS56103740A (en) Decimal divider
EP0316251A3 (en) Direct control facility for multiprocessor network
JPS5464496A (en) Fire detecting system