JPS5451427A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5451427A
JPS5451427A JP11752577A JP11752577A JPS5451427A JP S5451427 A JPS5451427 A JP S5451427A JP 11752577 A JP11752577 A JP 11752577A JP 11752577 A JP11752577 A JP 11752577A JP S5451427 A JPS5451427 A JP S5451427A
Authority
JP
Japan
Prior art keywords
ports
access
memory
access request
sequence control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11752577A
Other languages
Japanese (ja)
Inventor
Norio Aihara
Takashi Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11752577A priority Critical patent/JPS5451427A/en
Publication of JPS5451427A publication Critical patent/JPS5451427A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To enable to access a plural number of processing units efficiently for one memory, by providing the sequence control circuit.
CONSTITUTION: The sequence control circuit 13 memorizes the access request of ports 111 to 11n, and operates so that the access for the memory bank 14 can be made by sequentially designating the ports 111 to 11n depending on the priority. Further, when the circuit 13 all finishes the processing to the access request of the port memorized, the access request of the ports 111 to 11n at the time point is memorized and the sequence control is made. Further, the connection wires 121 to 12n connect each processor and the ports 111 to 11n and the order of operation of each port is controlled with the circuit 13, then while other ports perform memory access, a port receives the memory access request from the processing unit and the provision of the memory access can be made. Thus, the memory access can efficiently be made
COPYRIGHT: (C)1979,JPO&Japio
JP11752577A 1977-09-30 1977-09-30 Memory unit Pending JPS5451427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11752577A JPS5451427A (en) 1977-09-30 1977-09-30 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11752577A JPS5451427A (en) 1977-09-30 1977-09-30 Memory unit

Publications (1)

Publication Number Publication Date
JPS5451427A true JPS5451427A (en) 1979-04-23

Family

ID=14713930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11752577A Pending JPS5451427A (en) 1977-09-30 1977-09-30 Memory unit

Country Status (1)

Country Link
JP (1) JPS5451427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426268A (en) * 1987-07-22 1989-01-27 Fujitsu Ltd Priority control system in main storage access
JPH01201756A (en) * 1987-12-23 1989-08-14 Philips Gloeilampenfab:Nv Management system for preference of access to memory and use thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6426268A (en) * 1987-07-22 1989-01-27 Fujitsu Ltd Priority control system in main storage access
JPH01201756A (en) * 1987-12-23 1989-08-14 Philips Gloeilampenfab:Nv Management system for preference of access to memory and use thereof

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