JPS5621260A - Access unit - Google Patents

Access unit

Info

Publication number
JPS5621260A
JPS5621260A JP9575779A JP9575779A JPS5621260A JP S5621260 A JPS5621260 A JP S5621260A JP 9575779 A JP9575779 A JP 9575779A JP 9575779 A JP9575779 A JP 9575779A JP S5621260 A JPS5621260 A JP S5621260A
Authority
JP
Japan
Prior art keywords
output
lock
address
group
register group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9575779A
Other languages
Japanese (ja)
Inventor
Masahiko Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9575779A priority Critical patent/JPS5621260A/en
Publication of JPS5621260A publication Critical patent/JPS5621260A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To effectively use the memory module and to increase the system performance, by taking the lock flag and the lock address as a pair and providing the register group respectively storing a plurality of pairs.
CONSTITUTION: When the access address 101 is output, the comparator 2 compares the access address 101 with the lock address group 105 of the register group 1, and if in agreement, the coincidence output 103 is output. Further, the selection unit 3 inputs the lock flag output group 106 of the register group 1, and if there is any falg not set, one is selected with the preset condition and the selection output 104 is output. Further, the control circuit 4 inputs the access condition 102, and if the lock request is made, the coincidence output 103 and the selection output 104 are checked, and if the selected output is present, the set instruction 109 is output to the register group 1, and the address with request is set to the selected register at the selected output 104. Simultaneously, the lock flag is set, the approved output 107 is returned and the satisfaction of lock request is informed.
COPYRIGHT: (C)1981,JPO&Japio
JP9575779A 1979-07-27 1979-07-27 Access unit Pending JPS5621260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9575779A JPS5621260A (en) 1979-07-27 1979-07-27 Access unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9575779A JPS5621260A (en) 1979-07-27 1979-07-27 Access unit

Publications (1)

Publication Number Publication Date
JPS5621260A true JPS5621260A (en) 1981-02-27

Family

ID=14146356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9575779A Pending JPS5621260A (en) 1979-07-27 1979-07-27 Access unit

Country Status (1)

Country Link
JP (1) JPS5621260A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478358A (en) * 1987-09-19 1989-03-23 Canon Kk Data communication system
JPH06103155A (en) * 1991-04-04 1994-04-15 Northern Telecom Ltd Method and device for controlling shared memory
JPH07262140A (en) * 1994-03-16 1995-10-13 Nec Corp Exclusive controller
JP2004503864A (en) * 2000-06-12 2004-02-05 ミップス　テクノロジーズ　インコーポレイテッド Method and apparatus for realizing the atomicity of memory operations in a dynamic multi-streaming processor
US7926062B2 (en) 1998-12-16 2011-04-12 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131232A (en) * 1975-05-12 1976-11-15 Toshiba Corp Computer composit system
JPS52113645A (en) * 1976-03-19 1977-09-22 Toshiba Corp Data control system in multiple information processing system
JPS542034A (en) * 1977-06-08 1979-01-09 Hitachi Ltd Common file access system in multiplex computer system
JPS55108069A (en) * 1979-02-13 1980-08-19 Nippon Telegr & Teleph Corp <Ntt> Multiprocessor processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131232A (en) * 1975-05-12 1976-11-15 Toshiba Corp Computer composit system
JPS52113645A (en) * 1976-03-19 1977-09-22 Toshiba Corp Data control system in multiple information processing system
JPS542034A (en) * 1977-06-08 1979-01-09 Hitachi Ltd Common file access system in multiplex computer system
JPS55108069A (en) * 1979-02-13 1980-08-19 Nippon Telegr & Teleph Corp <Ntt> Multiprocessor processing system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478358A (en) * 1987-09-19 1989-03-23 Canon Kk Data communication system
JPH06103155A (en) * 1991-04-04 1994-04-15 Northern Telecom Ltd Method and device for controlling shared memory
JPH07262140A (en) * 1994-03-16 1995-10-13 Nec Corp Exclusive controller
US7926062B2 (en) 1998-12-16 2011-04-12 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US8468540B2 (en) 1998-12-16 2013-06-18 Bridge Crossing, Llc Interrupt and exception handling for multi-streaming digital processors
JP2004503864A (en) * 2000-06-12 2004-02-05 ミップス　テクノロジーズ　インコーポレイテッド Method and apparatus for realizing the atomicity of memory operations in a dynamic multi-streaming processor
JP4926364B2 (en) * 2000-06-12 2012-05-09 ミップス テクノロジーズ インコーポレイテッド Method and apparatus for realizing atomicity of memory operations in a dynamic multistreaming processor

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