JPS55108069A - Multiprocessor processing system - Google Patents

Multiprocessor processing system

Info

Publication number
JPS55108069A
JPS55108069A JP1530979A JP1530979A JPS55108069A JP S55108069 A JPS55108069 A JP S55108069A JP 1530979 A JP1530979 A JP 1530979A JP 1530979 A JP1530979 A JP 1530979A JP S55108069 A JPS55108069 A JP S55108069A
Authority
JP
Japan
Prior art keywords
far
processors
registers
address
interlocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1530979A
Other languages
Japanese (ja)
Inventor
Shizuo Shiokawa
Hideki Fukuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1530979A priority Critical patent/JPS55108069A/en
Publication of JPS55108069A publication Critical patent/JPS55108069A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the system processing ability, by minimizing the number of interlocks through the recognition that the same table is used by other processors.
CONSTITUTION: The processors PUo...PUn are provided with the flag address registers FARo...FARm and the effectiveness display bits Vo...Vm representing the effectiveness, and the memory MEM has tables TBo, TBl as the area commonly used by the processors PUo...PUn. When the unit PUo interpretes the lock instruction, the memory address to be accessed and the flag address setting the registers FARo... FARm in the processor are compared. Further, as far as the address in agreement with the registers is present, no memory request is made and the access of other processors can not be interrupted. As a result, the number of interlocks is minimized to increase the processing ability of the system.
COPYRIGHT: (C)1980,JPO&Japio
JP1530979A 1979-02-13 1979-02-13 Multiprocessor processing system Pending JPS55108069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1530979A JPS55108069A (en) 1979-02-13 1979-02-13 Multiprocessor processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1530979A JPS55108069A (en) 1979-02-13 1979-02-13 Multiprocessor processing system

Publications (1)

Publication Number Publication Date
JPS55108069A true JPS55108069A (en) 1980-08-19

Family

ID=11885183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1530979A Pending JPS55108069A (en) 1979-02-13 1979-02-13 Multiprocessor processing system

Country Status (1)

Country Link
JP (1) JPS55108069A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621260A (en) * 1979-07-27 1981-02-27 Nec Corp Access unit
JPS60144855A (en) * 1983-12-30 1985-07-31 Hitachi Ltd Memory lock system
JPS62214466A (en) * 1986-03-17 1987-09-21 Fujitsu Ltd Lock control system for storage device
JPH03196249A (en) * 1989-12-25 1991-08-27 Hitachi Ltd Multiple processor system
JPH05506336A (en) * 1988-12-02 1993-09-16 コーデックス　コーポレーション Applied rate control for echo canceling modems

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5621260A (en) * 1979-07-27 1981-02-27 Nec Corp Access unit
JPS60144855A (en) * 1983-12-30 1985-07-31 Hitachi Ltd Memory lock system
JPS62214466A (en) * 1986-03-17 1987-09-21 Fujitsu Ltd Lock control system for storage device
JPH05506336A (en) * 1988-12-02 1993-09-16 コーデックス　コーポレーション Applied rate control for echo canceling modems
JPH03196249A (en) * 1989-12-25 1991-08-27 Hitachi Ltd Multiple processor system

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