JPS5528114A - Display system of program execution level - Google Patents

Display system of program execution level

Info

Publication number
JPS5528114A
JPS5528114A JP9925278A JP9925278A JPS5528114A JP S5528114 A JPS5528114 A JP S5528114A JP 9925278 A JP9925278 A JP 9925278A JP 9925278 A JP9925278 A JP 9925278A JP S5528114 A JPS5528114 A JP S5528114A
Authority
JP
Japan
Prior art keywords
level
interruption
processing routine
program execution
psw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9925278A
Other languages
Japanese (ja)
Inventor
Kunikazu Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP9925278A priority Critical patent/JPS5528114A/en
Publication of JPS5528114A publication Critical patent/JPS5528114A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To display the types of programs under execution at present, by providing the program execution level display section and displaying the level of interruption processing routine with the program execution level display section, when the interruption processing routine is under execution.
CONSTITUTION: Assuming that the interruption request flag of level 0 is ON and the interruption mask of level 0 is also ON, the central processing unit accesses the address 1070 of new PSW being the interruption vector of level 0 and the new PSW is set to the PSW register. Since the output of level 0 of the interruption request flag register 1, that of the interruption mask register 2, and that of the access decoder 3 are all logically 1, FF 6-0 is set and it is diaplayed that the interrruption processing routine of level 0 is under execution. When the interruption processing routine is finished, the address 2000 of the old PSW is accessed and FF 6-0 is returned.
COPYRIGHT: (C)1980,JPO&Japio
JP9925278A 1978-08-15 1978-08-15 Display system of program execution level Pending JPS5528114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9925278A JPS5528114A (en) 1978-08-15 1978-08-15 Display system of program execution level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9925278A JPS5528114A (en) 1978-08-15 1978-08-15 Display system of program execution level

Publications (1)

Publication Number Publication Date
JPS5528114A true JPS5528114A (en) 1980-02-28

Family

ID=14242507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9925278A Pending JPS5528114A (en) 1978-08-15 1978-08-15 Display system of program execution level

Country Status (1)

Country Link
JP (1) JPS5528114A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56168218A (en) * 1980-12-19 1981-12-24 Idec Izumi Corp Process step-forward type sequence controller
JPS6263246A (en) * 1985-08-13 1987-03-19 ブランズウイツク　コ−ポレ−シヨン Shifting mechanism with clutch device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49130647A (en) * 1973-04-16 1974-12-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49130647A (en) * 1973-04-16 1974-12-14

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56168218A (en) * 1980-12-19 1981-12-24 Idec Izumi Corp Process step-forward type sequence controller
JPS6236567B2 (en) * 1980-12-19 1987-08-07 Izumi Denki Kk
JPS6263246A (en) * 1985-08-13 1987-03-19 ブランズウイツク　コ−ポレ−シヨン Shifting mechanism with clutch device

Similar Documents

Publication Publication Date Title
JPS5576447A (en) Address control system for software simulation
JPS55112651A (en) Virtual computer system
JPS5220735A (en) Microprogram controlled computer system
JPS5436138A (en) Direct memory access system
JPS5528114A (en) Display system of program execution level
JPS5334442A (en) Multi-processor system
JPS5588157A (en) Multi-work station processing system
JPS6472237A (en) Address calculation system
JPS54107647A (en) Data processor
JPS53113446A (en) Information processor and its method
JPS5520550A (en) Audio apparatus
JPS55108069A (en) Multiprocessor processing system
JPS5563455A (en) Memory system
JPS5617441A (en) Program interruption system
JPS5619153A (en) Virtual computer system
JPS5346245A (en) Microprogram controller
JPS55108052A (en) Data processing system
JPS55119724A (en) Priority selection circuit
JPS57111639A (en) Program debugging system
JPS5556253A (en) Data processor
JPS53140948A (en) Interrupt processing system
JPS54105939A (en) Information processor
JPS5319736A (en) Priority level determination and its unit
JPS556649A (en) Data processor with control program processing supervising function
JPS5561858A (en) Central operation control unit