JPS55110351A - Backup system between data processors - Google Patents

Backup system between data processors

Info

Publication number
JPS55110351A
JPS55110351A JP1764179A JP1764179A JPS55110351A JP S55110351 A JPS55110351 A JP S55110351A JP 1764179 A JP1764179 A JP 1764179A JP 1764179 A JP1764179 A JP 1764179A JP S55110351 A JPS55110351 A JP S55110351A
Authority
JP
Japan
Prior art keywords
tag
cpu
list
backup system
master list
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1764179A
Other languages
Japanese (ja)
Inventor
Shigeru Yamamoto
Shinichi Takigishi
Tadahiko Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP1764179A priority Critical patent/JPS55110351A/en
Publication of JPS55110351A publication Critical patent/JPS55110351A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To realize a backup system which is excellent in memory efficiency and consists of a small number of processes by storing a tag list in one CPU while giving common tag numbers, and then by providing a master list while determining charge range and backup relation.
CONSTITUTION: Higher CPUμA has a tag list with tag numbers put together for every nest in a main memory. According to those tag numbers, the charge range of the higher CPU is determined. Additionally, higher CPUμA has the main memory provided with a control master list, and main memories of lower CPU's μB1 to μB4 also provided with a tag control master list respectively. Then, the control master list is arrayed in the same order as tag numbers and tag lists and the backup system employing a control loop controlled by CPU's μA and μB1WμB4 is applied here.
COPYRIGHT: (C)1980,JPO&Japio
JP1764179A 1979-02-16 1979-02-16 Backup system between data processors Pending JPS55110351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1764179A JPS55110351A (en) 1979-02-16 1979-02-16 Backup system between data processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1764179A JPS55110351A (en) 1979-02-16 1979-02-16 Backup system between data processors

Publications (1)

Publication Number Publication Date
JPS55110351A true JPS55110351A (en) 1980-08-25

Family

ID=11949480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1764179A Pending JPS55110351A (en) 1979-02-16 1979-02-16 Backup system between data processors

Country Status (1)

Country Link
JP (1) JPS55110351A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816301A (en) * 1981-07-22 1983-01-31 Hitachi Ltd Switch controlling system of multiplex system
JPS6136801A (en) * 1984-07-30 1986-02-21 Toshiba Corp Decentralized controller
JPS6152701A (en) * 1984-08-23 1986-03-15 Hitachi Ltd Multiplexing controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816301A (en) * 1981-07-22 1983-01-31 Hitachi Ltd Switch controlling system of multiplex system
JPS6136801A (en) * 1984-07-30 1986-02-21 Toshiba Corp Decentralized controller
JPS6152701A (en) * 1984-08-23 1986-03-15 Hitachi Ltd Multiplexing controller

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