JPS55154653A - Interruption distributing system to multiprocessor - Google Patents

Interruption distributing system to multiprocessor

Info

Publication number
JPS55154653A
JPS55154653A JP6302779A JP6302779A JPS55154653A JP S55154653 A JPS55154653 A JP S55154653A JP 6302779 A JP6302779 A JP 6302779A JP 6302779 A JP6302779 A JP 6302779A JP S55154653 A JPS55154653 A JP S55154653A
Authority
JP
Japan
Prior art keywords
interruption
circuit
request
input
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6302779A
Other languages
Japanese (ja)
Other versions
JPS6131904B2 (en
Inventor
Hiroshi Funashige
Kenichi Yukimatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6302779A priority Critical patent/JPS55154653A/en
Publication of JPS55154653A publication Critical patent/JPS55154653A/en
Publication of JPS6131904B2 publication Critical patent/JPS6131904B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the time required for interruption distribution and to increase the interruption processing efficiency, by excluding the managing use CPU of multiprocessor of load scattering type and executing the interruption simultaneous and parallel processing easily.
CONSTITUTION: To an interruption request reception circuit 100, timer interruption request, interruption request between CPUs, console interruption request and input and output system interruption request are input in the order of higher priority, and one of the interruption request received at the circuit 100 is fed to a distribution circuit 150. If this interruption is other than the input and output system, the circuit 150 is operated according to the instruction of an interrupted address instruction circuit 140 and interruption is made to a designated CPU, and if the interruption is the request to input and output system, an circulation instruction circuit 110 is operative according to the instruction of the circuit 110 and interruption is made to the designated CPU. The circuit 110 is connected with a circulation skip control unit 120 connected to an interruption disable condition detection circuit 130, and the interruption request is simultaneously in parallel processing to reduce the time required for interruption distribution.
COPYRIGHT: (C)1980,JPO&Japio
JP6302779A 1979-05-22 1979-05-22 Interruption distributing system to multiprocessor Granted JPS55154653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6302779A JPS55154653A (en) 1979-05-22 1979-05-22 Interruption distributing system to multiprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6302779A JPS55154653A (en) 1979-05-22 1979-05-22 Interruption distributing system to multiprocessor

Publications (2)

Publication Number Publication Date
JPS55154653A true JPS55154653A (en) 1980-12-02
JPS6131904B2 JPS6131904B2 (en) 1986-07-23

Family

ID=13217426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6302779A Granted JPS55154653A (en) 1979-05-22 1979-05-22 Interruption distributing system to multiprocessor

Country Status (1)

Country Link
JP (1) JPS55154653A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143670A (en) * 1981-03-03 1982-09-04 Nec Corp Parallel processing system
JPS6292058A (en) * 1985-10-18 1987-04-27 Fujitsu Ltd Multiprocessor system
JPS6446155A (en) * 1987-08-13 1989-02-20 Fujitsu Ltd Interruption control system
JP2014524626A (en) * 2011-08-23 2014-09-22 サムスン エレクトロニクス カンパニー リミテッド Interrupt allocation method and apparatus for multi-core system
CN106095548A (en) * 2016-06-03 2016-11-09 青岛海信移动通信技术股份有限公司 A kind of method and apparatus distributing interruption in multi-core processor system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167203U (en) * 1984-10-11 1986-05-08

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57143670A (en) * 1981-03-03 1982-09-04 Nec Corp Parallel processing system
JPS6292058A (en) * 1985-10-18 1987-04-27 Fujitsu Ltd Multiprocessor system
JPS6446155A (en) * 1987-08-13 1989-02-20 Fujitsu Ltd Interruption control system
JP2014524626A (en) * 2011-08-23 2014-09-22 サムスン エレクトロニクス カンパニー リミテッド Interrupt allocation method and apparatus for multi-core system
JP2017162522A (en) * 2011-08-23 2017-09-14 サムスン エレクトロニクス カンパニー リミテッド Method and apparatus for allocating interrupts in multi-core system
CN106095548A (en) * 2016-06-03 2016-11-09 青岛海信移动通信技术股份有限公司 A kind of method and apparatus distributing interruption in multi-core processor system

Also Published As

Publication number Publication date
JPS6131904B2 (en) 1986-07-23

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