JPS569847A - Instruction retry processing control system - Google Patents

Instruction retry processing control system

Info

Publication number
JPS569847A
JPS569847A JP8495379A JP8495379A JPS569847A JP S569847 A JPS569847 A JP S569847A JP 8495379 A JP8495379 A JP 8495379A JP 8495379 A JP8495379 A JP 8495379A JP S569847 A JPS569847 A JP S569847A
Authority
JP
Japan
Prior art keywords
signal
instruction
control memory
gate
fault detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8495379A
Other languages
Japanese (ja)
Inventor
Tsuguo Hatsuda
Tsutomu Sumimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8495379A priority Critical patent/JPS569847A/en
Publication of JPS569847A publication Critical patent/JPS569847A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the reliability of a unit by performing processing with efficiency, by sending an instruction-retry disability signal only when the AND condition of a control memory fault detection signal and request signal to a memory and channel is met.
CONSTITUTION: Output signals of parity checking circuits 6F and 6C for fields F and C of control memory read register 3 set control memory fault detection FF7F, 7C and through OR gate 14, control memory fault detection signal (f) is output. Next, this signal (f) and a signal from OR gate 10 performing OR of a request signal to a memory and channel are input to AND gate 11 and only when AND is established, an instruction retry disability signal is sent out. At the same time, the instruction retry processing is inhibited and unrecoverable fault generation interruption starts immediately. When this signal is not sent out, the instruction retry processing is performed as usual.
COPYRIGHT: (C)1981,JPO&Japio
JP8495379A 1979-07-06 1979-07-06 Instruction retry processing control system Pending JPS569847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8495379A JPS569847A (en) 1979-07-06 1979-07-06 Instruction retry processing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8495379A JPS569847A (en) 1979-07-06 1979-07-06 Instruction retry processing control system

Publications (1)

Publication Number Publication Date
JPS569847A true JPS569847A (en) 1981-01-31

Family

ID=13844990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8495379A Pending JPS569847A (en) 1979-07-06 1979-07-06 Instruction retry processing control system

Country Status (1)

Country Link
JP (1) JPS569847A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57124339A (en) * 1981-01-24 1982-08-03 Hitachi Medical Corp Automatic exposure controller for x-ray
JPS6269327A (en) * 1985-09-24 1987-03-30 Hitachi Ltd Automatic recovery system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57124339A (en) * 1981-01-24 1982-08-03 Hitachi Medical Corp Automatic exposure controller for x-ray
JPS6269327A (en) * 1985-09-24 1987-03-30 Hitachi Ltd Automatic recovery system

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